www..comMCF5206E UM/D, rev.1MCF5206E ColdFireMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com iiiMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E ColdFire(R) Integrated Microprocessor User's Manual describes the programming, capabilities, and operation of the MCF5206E device. Refer to the ColdFire Family Programmer's Reference Manual Rev 1.0 (MCF5200PRMREV1/D) for information on the ColdFire Family of microprocessors. CONTENTS This user manual is organized as follows: Section 1: Introduction Section 2: Signal Description Section 3: ColdFire Core Section 4: Instruction Cache Section 5: SRAM Section 6: Bus Operation Section 7: DMA Controller Module Section 8: System Integration Module (SIM) Section 9: Chip-Select Module Section 10: Parallel Port (General-Purpose I/O) Module Section 11: DRAM Controller Section 12: UART Modules Section 13: M-Bus Module .com Section 14: Timer Module Section 15: Debug Support Section 16: IEEE 1149.1 Test Access Port (JTAG) Section 17: Electrical Characteristics Section 18: Mechanical Characteristics Appendix A: MCF5206E Memory Map Appendix B: Porting from M68000 IndexMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com vMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Memory Map Appendix B: Porting from M68000 A BMCF5206E Memory Map Appendix B: Porting from M68000MCF5206E Features ............................................................................1-2 Functional Blocks .................................................................................1-4 ColdFire Processor Core ............................................................1-5 Processor States ............................................................1-6 Programming Model .......................................................1-6 MAC Registers Summary .............................................1-10 Addressing Capabilities Summary ................................1-10 Instruction Set Overview ...............................................1-10 MAC Module .............................................................................1-15 Hardware Divide Module ..........................................................1-15 Instruction Cache .....................................................................1-15 Internal SRAM ..........................................................................1-15 .com DRAM Controller ......................................................................1-16 Direct Memory Access (DMA) ..................................................1-16 UART Modules .........................................................................1-16 Timer Module ...........................................................................1-16 Motorola Bus (M-Bus) Module ..................................................1-16 System Interface ......................................................................1-17 External Bus Interface ..................................................1-17 Chip Selects ..................................................................1-17 8-Bit Parallel Port (General Purpose I/O) .................................1-17 Interrupt Controller ...................................................................1-17 System Protection ....................................................................1-18 JTAG ........................................................................................1-18 System Debug Interface ...........................................................1-18 Pinout and Package .................................................................1-18 Section 2 Signal Description 2.1 2.2 2.2.1 2.2.2 2.2.3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com viiMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com ixMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xiMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xiiiMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E BSDL Description .............................................16-9 Obtaining the IEEE 1149.1 Standard .................................................16-9 Section 17 Electrical CharacteristicsMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xixMCF5206E Memory Map Summary Appendix B .com Porting From M68000 Family DevicesMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxiMCF5206E Block Diagram ............................................................................... 1-4 Programming Model........................................................................................ 1-8 ColdFire Processor Core Pipelines .................................................................. User Programming Model ................................................................................ MAC Unit User Programming Model................................................................ Supervisor Programming Model....................................................................... Exception Stack Frame Form........................................................................... 3-1 3-3 3-4 3-4 3-7MCF5206E Interface to Various Port Sizes...................................................... 6-8 Byte-, Word-, and Longword-Read Transfer Flowchart ................................. 6-11 Longword-Read Transfer From a 32 bit Port (No Wait States) ...................... 6-12 Byte-, Word-, and Longword-Write Transfer Flowchart.................................. 6-14 Word-Write Transfer to a 16 bit Port (No Wait States)................................... 6-15 Bursting Word-, Longword-, and Line-Read Transfer Flowchart.................... 6-17 Bursting Word-Read From an 8 bit Port (No Wait States) ............................. 6-18 Word-, Longword-, and Line-Write Transfer Flowchart .................................. 6-20 Line-Write Transfer to a 32 bit Port (No Wait States)..................................... 6-21 Burst-Inhibited Word-, Longword-, and Line-Read Transfer Flowchart.......... 6-24 Burst-Inhibited Longword Read From an 8 bit Port (No Wait States) ............ 6-25 Burst-Inhibited Byte-, Word-, and Longword-Write Transfer Flowchart ......... 6-27 Burst-Inhibited Longword-Write Transfer to a 16 bit Port (No Wait States)............................................................................................. 6-28 Byte-, Word-, and Longword-Read Transfer Flowchart ................................. 6-30 Byte-Read Transfer from an 8-Bit Port Using Async. Termination............ 6-31 Byte-, Word-, and Longword-Write Transfer Flowchart................................ 6-32 Byte-Write Transfer to a 32-Bit Port Using Async. Termination .....................6-33 Bursting Word-, Longword-, and Line-Read Transfer Flowchart ....................6-35 Bursting Longword-Read from 16 bit Port ......................................................6-36 Word-, Longword-, and Line-Write Transfer Flowchart ...................................6-38 Bursting Line-Write from 32 bit Port Using Async. Termination ....................6-39 Burst-Inhibited Word-, Longword-, and Line-Read Transfer Flowchart ..........6-42MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Two-Wire Mode Bus Arbitration Interface ................................... 6-55 Two-Wire Implicit and Explicit Bus Ownership............................................... 6-57 Two-Wire Bus Arbitration with Bus Lock Negated ......................................... 6-58 Two-Wire Bus Arbitration with Bus Lock Asserted......................................... 6-59 MCF5206E Two-Wire Bus Arbitration Protocol State Diagram ...................... 6-60 Three-Wire Implicit and Explicit Bus Ownership ............................................ 6-63 Three-Wire Bus Arbitration with Bus Lock Bit Asserted................................. 6-64 MCF5206E Bus Arbitration Protocol State Diagram ...................................... 6-65 Alternate Master Read Transfer using MCF5206E -Generated Transfer Acknowledge Flowchart................................................................... 6-70 Alternate Master Read Transfer...................................................................... 6-71 .com Alternate Master Write Transfer..................................................................... 6-72 Alternate Master Write Transfer Using Transfer-Acknowledge Timing ......... 6-73 Alternate Master Bursting Read Transfer Flowchart ...................................... 6-75 Alternate Master Bursting Longword Read Transfer to an 8 bit Port ............ 6-76 Alternate Master Bursting Write Transfer Flowchart ...................................... 6-79 Alternate Master Bursting Longword Write Transfer to a 16 bit Port ............. 6-80 Master Reset Timing...................................................................................... 6-82 Normal Reset Timing ..................................................................................... 6-83 Software Watchdog Timer Reset Timing ....................................................... 6-84 DMA Signal Diagram ....................................................................................... 7-2 Single-Address Transfers ................................................................................ 7-5 Dual-Address Transfer..................................................................................... 7-5 DMA Controller Module Register Model Per Channel ..................................... 7-6 External Request Timing - Cycle-Steal Mode, Single-Address Mode............ 7-15 External Request Timing - Cycle-Steal Mode, Dual-Address Mode .............. 7-16 MCF5206E Interface to Various Port Sizes...................................................... 9-4 Longword Write Transfer from a 32 bit Port .................................................... 9-9 Word Write Transfer to a 16 bit Port ............................................................... 9-10 Byte Write Transfer from an 8 bit Port .......................................................... 9-12 Longword Burst Read Transfer from a 16 bit Port ......................................... 9-14MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxiiiMCF5206E Interface to Various Port Sizes.................................................... 11-4 Address Multiplexing For 8-bit DRAM With 512 Byte Page Size ................... 11-9 Connection Diagram for 4MByte DRAM with 8 bit Port and 1 KByte Page.. 11-15 .com Connection Diagram for 1MByte DRAM with 8 bit Port and 1 KByte Page.. 11-15 Byte Read Transfers in Normal Mode with 8 bit DRAM ...............................11-17 Longword Write Transfer in Normal Mode with 16 bit DRAM ...................... 11-19 Word Write Transfer in Fast Page Mode with 8 Bit DRAM .......................... 11-22 Longword Read Transfer Followed by a Page Hit Longword Read Transfer in Fast Page Mode with 32 bit DRAM ...................................................................... 11-24 Word Write Transfer Followed by a Page-Hit Word Write Transfer in Fast Page Mode with 16 bit DRAM ......................................................................................... 11-26 Byte Read Transfer Followed by a Page-Miss Byte Read Transfer in Fast Page Mode with 8 bit DRAM ................................................................................. 11-28 Bus Arbitration in Fast Page Mode .............................................................. 11-31 Longword Write Transfer Followed by a Word Read Transfer in Burst Page Mode with 16 bit DRAM ......................................................................................... 11-33 Word Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page Mode with 8 bit EDO DRAM......................................................................... 11-36 Alternate Master Byte Read Transfer Followed by Byte Write Transfer in Normal Mode with 16 bit DRAM ............................................................................... 11-42 Alt. Master Longword Write Transfer in Normal Mode with 16 bit DRAM ....11-45 Alt. Master Word Read Transfer in Burst Page Mode with 8 bit DRAM ....... 11-48 Normal Mode DRAM Transfer Timing.......................................................... 11-53 Fast Page Mode or Burst Page Mode DRAM Transfer Timing .................... 11-54 Fast Page Mode or Burst Page Mode DRAM Transfer Timing .................... 11-54MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Package Diagram & Pinout ..........................................................18-2MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxvMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Data Formats ................................................................. 1-9 Instruction Set Summary.............................................................................. 1-10 MCF5206E Signal Index................................................................................. 2-2 Address Bus.................................................................................................... 2-3 Byte Write-Enable Signals ............................................................................. 2-6 Interrupt Levels for Encoded External Interrupts..............................................2-7 Boot CS[0] Automatic Acknowledge (AA) Enable ........................................... 2-8 Interrupt Request Encodings for CS[0] ........................................................... 2-8 Data Transfer Size Encoding .......................................................................... 2-9 Bus Cycle Transfer Type Encoding................................................................. 2-9 ATM Encoding................................................................................................ 2-9 CAS Assertion.............................................................................................. 2-13 .com Processor Status Encodings ......................................................................... 2-16 MCF5206E Signal Summary ........................................................................ 2-19 Exception Vector Assignments ....................................................................... 3-7 Format Field Encodings .................................................................................. 3-8 Fault Status Encodings ................................................................................... 3-8 Misaligned Operand References.................................................................. 3-12 Move Byte and Word Execution Times ......................................................... 3-13 Move Long Execution Times........................................................................ 3-13 One-Operand Instruction Execution Times ................................................... 3-14 Two-Operand Instruction Execution Times ................................................... 3-15 Miscellaneous Instruction Execution Times .................................................. 3-17 General Branch Instruction Execution Times................................................ 3-18 BRA, Bcc Instruction Execution Times.......................................................... 3-18 Initial Fetch Offset vs. CLNF Bits .................................................................... 4-4 Instruction Cache Operation as Defined by CACR[31,10] ..............................4-5 Memory Map of I-Cache Registers ................................................................. 4-6 External Fetch Size Based on Miss Address and CLNF................................. 4-8MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxviiMCF5206E Two-Wire Bus Arbitration Protocol Transition Conditions .......... 6-59 MCF5206E Two-Wire Arbitration Protocol State Diagram ............................ 6-60 MCF5206E Three-Wire Bus Arbitration Protocol Transition Conditions....... 6-65 MCF5206E Three-Wire Arbitration Protocol State Diagram.......................... 6-66 Signal Source During Alternate Master Accesses ........................................ 6-69 DMA Signals .................................................................................................... 7-3 DMA Controller Module Channel Offsets......................................................... 7-6 BWC Encoding ................................................................................................ 7-9 SSIZE Encoding............................................................................................ 7-10 DSIZE Encoding ........................................................................................... 7-10 Interrupt Levels for Encoded External Interrupts ............................................ 8-4 Memory Map of SIM Registers ....................................................................... 8-7 Interrupt Control Register Assignments ........................................................ 8-10 Interrupt Mask Register Bit Assignments..................................................... 8-11 Interrupt Pending Register Bit Assignments ................................................ 8-12 SWT Timeout Period..................................................................................... 8-15 Bus Monitor Timeout Periods........................................................................ 8-15 PAR3 - PAR0 Pin Assignment ..................................................................... 8-17 Arbitration Control Encodings (ARBCTRL) .................................................... 8-19MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxixMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Package/Frequency Availability .................................................. 18-3 MCF5206E Documentation ............................................................................ 18-3MCF5206E User Programming Model ............................................................. A-iMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com xxxiMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E integrated microprocessor combines a Version 2 (V2) ColdFire(R) processor core with several peripheral functions such as a DRAM controller, timers, general-purpose I/O and serial interfaces, debug module, and system integration. Designed for embedded control applications, the V2 ColdFire core delivers enhanced performance while maintaining low system costs. To speed program execution, the largeon-chip instruction cache and SRAM provide one-cycle access to critical code and data. The MCF5206E greatly reduces the time required for system design and implementation by packaging common system functions on chip and providing glueless interfaces to 8 bit, 16 bit, and 32 bit DRAM, SRAM, ROM, and I/O devices. The MCF5206E is an enhanced version of the MCF5206 processor, with the same peripheral set, DMA, MAC, Hardware Divide, larger cache, and larger SRAM. It is pin compatible with the MCF5206, with the DMA pins muxed with Timer 0 pins. Available in 3.3V, with 5V- tolerant I/O, at speeds of 45 MHz and 54 MHz; higher performance at a lower .com price. The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume markets new levels of price and performance. Based on the concept of variable-length RISC technology, ColdFire combines the architectural simplicity of conventional 32 bit RISC with a memory-saving, variable-length instruction set. In defining the ColdFire architecture for embedded processing applications, Motorola incorporated RISC architecture for peak performance and a simplified version of the variable-length instruction set found in the M68000 Family for code density and programmer familiarity. By incorporating a variable-length instruction set architecture, embedded processor designers using ColdFire processors will enjoy significant system-level advantages over conventional 32-bit fixed-length RISC architectures. The denser binary code for ColdFire processors consumes less valuable memory than any 32-bit fixed-length instruction set RISC processor available. This improved code density means more efficient system memory use for a given application and requires slower, less costly memory to help achieve a target performance level. The integrated peripheral functions provide high performance and flexibility. For starters, the DRAM controller supports as much as 512 Mbytes of DRAM. The MCF5206E supports both page-mode and extended-data-out DRAMs. Two channels of DMA allow for fast data transfer using a programmable burst mode independent of processor execution. The serial interfaces consist of two programmable full duplex UARTs and a separate I2C1 -compatible Motorola bus (M-Bus interface). The two 16-bit general-purpose multimode timers provideMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-1MCF5206E FEATURESMCF5206E integrated processor include the following: * Version 2 ColdFire Processor CoreMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-3MCF5206E processor. The paragraphs that followMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Block DiagramMCF5206E also includes MAC and hardware divide instructions which enhance the mathematical performance.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-5MCF5206E processor cannot complete the transition to normal processing nor can it save the internal machine state. The processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. When the processor executes a STOP instruction, it is in a special type of normal processing state, e.g., one without bus cycles. The processor stops but it does not halt.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA MODE FIELD 000 001 010 011 100 101 110 111 111 111 111 111 REG. FIELD reg. no. reg. no. reg. no. reg. no. reg. no. reg. no. reg. no. 010 011 000 001 100 CATEGORY DATA X -- X X X X X X X X X X MEMORY -- -- X X X X X X X X X X CONTROL -- -- X -- -- X X X X X X -- ALTERABLE X X X X X X X -- -- -- -- --MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E device is executing, and the lower byte of the SR, which is accessible as the Condition Code Register (CCR). The CCR contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-9MCF5206E data formats. Table 1-2. MCF5206E Data FormatsMCF5206E processor supports seven addressing modes. The register indirect addressing modes support postincrement, .com predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated embedded applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required to support position-independent software. Besides these addressing modes, the MCF5206E processor provides index scaling features. An instruction's addressing mode can specify the value of an operand or a register containing the operand. It can also specify how to derive the effective address of an operand in memory. Each addressing mode has an assembler syntax. Some instructions imply the addressing mode for an operand. These instructions include the appropriate fields for operands that use only one addressing mode. Table 1-1 summarizes the specific effective addressing modes of ColdFire processors. Table 1-2 summarizes the MOVE specific effective addressing modes. 1.2.1.5 INSTRUCTION SET OVERVIEW. The ColdFire instruction set supports high-level languages and is optimized for those instructions embedded code most commonly executes. Table 1-3 lists the notational conventions used throughout this manual, unless otherwise specified. Table 1-4 provides an alphabetized listing of the ColdFire instruction set opcode, operation, and syntax. The left operand in the syntax is always the source operand and the right operand is the destination operand. This instruction set is a simplified version of the M68K instruction set. The removed instructions include BCD, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit result. In addition, nine new MAC instructions have been added.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA y,x + - x / ~ & | ^ << >> sign-extended If then else Logical Condition (example: NE for not equal) REGISTER OPERANDS Any Address Register n (example: A3 is address register 3) Source and destination address registers, respectively Any Data Register n (example: D5 is data register 5) Source and destination data registers, respectively Any Address or Data Register Any source and destination registers, respectively Any second destination register Any Control Register (example: VBR is the vector base register) REGISTER/PORT NAMES MAC Accumulator Debug Data Port Condition Code Register (lower byte of status register) MAC Status Register Mask Register Program Counter Processor Status Port Status Register MISCELLANEOUS OPERANDS Immediate data following the instruction word(s) Effective Address Source and Destination Effective Addresses, respectively .com Assembly Program Label List of registers (example: D3-D0) Operand data size: Byte (B), Word (W), Longword (L) OPERATIONSMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAx y,Dx y,Ax #,Dx #,x Dy,Dx Dy,x y,Dx #,Dx Dy,Dx #,Dx Dy,Dx ,Dx Dy,x #,x Dy,x #,x Dy,x #,x Dy,x #,x x #,Dx y,Dx y,Ax (Ax) y,Dx OPERAND SIZE 32 32 32 32 32 32 32 32 32 32 32 32 32 8,16 8,32 8,32 8,32 8,32 8,16 8,32 8,32 8,16 OPERATION) 0 MSB (Dx >> Dy) X/C MSB (Dx >> #) X/C If Condition True, Then PC + 2 + dn PC ~( of Destination) Z, Bit of Destination ~( of Destination) Z; 0 Bit of Destination PC + 2 + dn PC ~( of Destination) Z; 1 Bit of Destination SP - 4 SP; next sequential PC (SP); PC + 2 + dn PCy,Dxx #,Dx Dx Dx Dx none y,Ax Ax,# Dy,Dx #,Dx Dy,Dx #,Dx Ry,Rx Ry,Rx,y,Rw of Destination) Z 8,32 8,16,32 0 Destination .com 32 Destination - Immediate Data 32 Destination - Source 32 Destination - Source none Push and Invalidate Cache Line 16 Dx /y Dx {16-bit Remainder; 16-bit Quotient} 32 Dx /y Dx {32-bit Quotient} Signed operation 16 Dx /y Dx {16-bit Remainder; 16-bit Quotient} Dx /y Dx {32-bit Quotient} Unsigned operation 32 Source ^ Destination Destination 32 Immediate Data ^ Destination Destination 8 16 Sign-Extended Destination Destination 16 32 8 32 Sign-Extended Destination Destination none Enter Halted State none Address of PC 32 SP - 4 SP; next sequential PC (SP); PC 32 Ax 16 SP - 4 SP; Ax (SP); SP Ax; SP + d16 SP 32 X/C (Dx << Dy) 0 32 X/C (Dx << #) 0 32 0 (Dx >> Dy) X/C 32 0 (Dx >> #) X/C 16 x 16 + 32 32 ACC + (Ry x Rx){<< 1 | >> 1} ACC 32 32 ACC + (Ry x Rx){<< 1 | >> 1} ACC; (y{&MASK}) RwMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-13 Ry,Rx,y,Rw y,x ACC,Rx Dx MACSR,Rx MACSR,CCR MASK,Rx Dx Ry,ACC #,ACC Dy,CCR #,CCR Ry,MACSR #,MACSR Ry,MASK #,MASK Dy,SR #,SR y,Ax Ry,Rc list,x y,list #,Dx Ry,Rx Ry,Rx,y,Rw Ry,Rx Ry,Rx,y,Rw y,Dx y,Dx x x none Dy,x y,Dx #,Dx none y,Dx:Dw y,Dx:Dw none none Dx # Dy,x y,Dx y,Ax #,Dx #,x OPERAND SIZE 32 x 32 + 32 32 32 32 8,16,32 32 16 32 8 32 16 32 32 8 32 32 32 16 16,32 32 32 32 32 8 32 32 - 16 x 16 32 32 32 OPERATION ACC + (Ry x Rx){<< 1 | >> 1} ACC ACC + (Ry x Rx){<< 1 | >> 1} ACC; (y{&MASK}) Rw y x ACC Rx CCR Dx MACSR Rx MACSR CCR MASK Rx SR Dx Ry ACC # ACC Dy CCR # CCR Ry MACSR # MACSR Ry MASK # MASK Source SRy{&MASK}) Rw 32 - 32 x 32 32 ACC - (Ry x Rx){<< 1 | >> 1} ACC 32 32 ACC .com - (Ry x Rx){<< 1 | >> 1} ACC; (y{&MASK}) Rw 16 x 16 32 Source x Destination Destination 32 x 32 32 Signed operation 16 x 16 32 Source x Destination Destination 32 x 32 32 Unsigned operation 32 0 - Destination Destination 32 0 - Destination - X Destination none Synchronize Pipelines; PC + 2 PC 32 ~ Destination Destination 32 Source | Destination Destination 32 32 none 32 32 none none 8 16 32 32 32 32 32 Immediate Data | Destination Destination SP - 4 SP; Address of (SP) Set PST= $4 Dx/y Dw {32-bit Remainder} Signed operation Dx/y Dw {32-bit Remainder} Unsigned operation (SP+2) SR; SP+4 SP; (SP) PC; SP + FormatField SP (SP) PC; SP + 4 SP If Condition True, Then 1's Destination; Else 0's Destination Immediate Data SR; Enter Stopped State Destination - Source Destination Destination - Source Destination Destination - Immediate Data Destination Destination - Immediate data DestinationMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA y Ax y yy DDATA port y Debug ModuleMCF5206E processor includes a hardware divider which performs a number of interger divide operations. The supported divide functions include: 32/16 producing a 16-bit quotient .com and 16-bit remainder, 32/32 producing a 32-bit quotient, and 32/32 producing a 32-bit remainder. The hardware divide function provides enhanced functionality, particularly in printing applications. With graphics-based printing this has resulted in as much as 15 percent performance improvement.MCF5206E processor uses a 4K-byte, direct-mapped instruction cache to achieve 50 MIPS at 54MHz. The cache is accessed by physical addresses, where each 16-byte line consists of an address tag and a valid bit. The instruction cache also includes a bursting interface for 32 bit, 16 bit, and 8 bit port sizes to quickly fill cache lines.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-15MCF5206E DRAM controller provides a glueless interface for as many as two banks of DRAM, each of which can be from 128 Kbytes to 256 Mbytes in size. The controller supports an 8 bit, 16 bit, or 32 bit data bus. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in fast page mode, burst-page mode, or in normal mode, and supports EDO DRAMs. DRAM operations are available to other external bus masters. The DRAM controller can generate CAS and RAS for an external master and can continue to manage refresh requests.MCF5206E provides 2 fully programmable DMA channels for quick data transfer. Single- and dual-address mode is provided with the ability to program bursting and cycle steal. Data transfers are 32 bits in length with packing and unpacking supported, along with an auto-alignment option for efficient block transfers. DMA transfers can be initiated via three mechanisms: S/W initiated; external requests; or from a UART interrupt.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E processor provides a glueless interface to 8-, 16-, and 32-bit SRAM, ROM, and peripheral devices with independent programmable control of the assertion and negation of chip selects and write enables. Programmable address and data-hold times can be extended for a compatible interface to external devices and memory. The MCF5206E also supports bursting ROMs. 1.3.11.1 EXTERNAL BUS INTERFACE. The bus interface controller transfers information between the ColdFire core and memory, peripherals, or other masters on the external bus. The external bus interface provides as many as 28 bits of address bus space, a 32-bit data bus, and all associated control signals. This interface implements an extended synchronous protocol that supports bursting operations. For nonsynchronous external memory and peripherals, the MCF5206E processor provides an alternate asynchronous bus transfer acknowledgment signal. Simple two-wire request/acknowledge bus arbitration between the MCF5206E processor and another bus master, such as a DMA device, is glueless with arbitration handled internal to the MCF5206E processor. Alternately, an external bus arbiter can control more complex three-wire (request, grant, busy) multiple-master bus arbitration, allowing overlapped bus arbitration with one clock-bus handovers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 1-17MCF5206E processor contains a 16-bit software watchdog timer with an 8-bit prescaler. The programmable software watchdog timer provides either a level 7 interrupt or a hardware reset on timeout. The MCF5206E processor also contains a reset status register that indicates the cause of the last reset.MCF5206E processor includes dedicated user-accessible test logic that complies with the IEEE 1149.1 standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1 standard.MCF5206E device is supplied in a 160-pin plastic quad flat pack package, at speeds of 45 MHz and 54 MHz, and is pin-compatible with the MCF5206 (DMA is muxed with timer). It is available in 3.3V, with 5V-tolerant I/O.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E along with the signal interface. This section describes the MCF5206E input and output signals. The descriptions are grouped according to functionality (refer to Table 2-1).MCF5206E Block DiagramMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-1MCF5206E Signal IndexMCF5206E to request bus mastership Asserted by bus arbiter to grant bus mastership privileges to the MCF5206E Indicates the MCF5206E has assumed explicit bus mastership of the external bus Input used to clock internal logic Processor reset Row address strobe for external DRAM Column address strobe for external DRAM Asserted on DRAM write cycles and negated on DRAM read cycles Receive serial data input for UART 1 and UART 2 Transmit serial data output for UART 1 and UART 2 Indicates UART 1 is ready to receive data RTSindicates UART 2 is ready to receive data/ RSTO is the reset out signal Indicates can transmit serial data for UART 1 and UART 2MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Signal Index (Continued)MCF5206E as a slave DRAM controller, the external master asserts TS and places the transfer address on the address pins. The external master then three-states the address signals and the MCF5206E drives the row address and the column address on the address bus at the appropriate times.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-3MCF5206E outputs the address and increments the lower bits during burst transfers, allowing the address bus to be directly connected to external memory. For DRAM transfers initiated by the ColdFire core, the MCF5206E outputs the row address and column address as specified by the DRAM control registers. The MCF5206E does not output the address during alternate or external master initiated chip select and default memory transfers. When an external master is using the MCF5206E as a slave DRAM controller, the external master asserts TS and places the .com row and column address on the address pins. The external master drives the address signals to a high-impedence state and the MCF5206E then drives the row address and the column address on the address bus at the appropriate times.MCF5206E and all other devices in the system. During a read bus transfer, data is registered from the bus on the rising clock edge during which TA is asserted, or during the rising clock in which internal asynchronous transfer acknowledge is asserted or internal transfer acknowledge is asserted. The data bus port width is initially configured by the values on IPL[1]/IRQ[4] and IPL[0]/ IRQ[1] during reset. Port width is individually programmed for each chip select region and DRAM bank, and is globally configured for a memory region not matching chip select settings or DRAM memory, referred to as default memory. The data bus transfers byte, word, or longword sized data. All 32 bits of the data bus are driven during writes, regardless of port width or operand size.MCF5206E provides as many eight programmable chip selects that can directly interface with SRAM, EPROM, EEPROM, and peripherals.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E . During reset, these pins configure the processor for the number of wait states and port size for the boot chip select (CS[0]).MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-7MCF5206E monitors this signal to determine if chip select or DRAM control signals need to be asserted.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E monitors these signals to determine the data size for asserting the appropriate memory control signals. Table 2-7 shows the definitions of the SIZ[1:0] encoding.MCF5206E during alternate master transfers. Table 2-8 lists the definitions of the TT[1:0] encodings.MCF5206E during alternate master transfers. Table 2-9 lists the encoding for normal, debug and CPU space/interrupt-acknowledge transfer types.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-9MCF5206E asserts this three-state bidirectional active-low signal for one clock period to indicate the start of each bus cycle. During alternate master accesses, the MCF5206E monitors transfer start (TS) to detect the start of each alternate master bus cycle to determine if chip select or DRAM control signals need to be asserted.MCF5206E , transfer acknowledge (TA) is an input signal from the referenced slave device indicating completion of the transfer. TA is not used for termination during DRAM accesses initiated by the MCF5206E . When an external master is controlling the bus, TA may be driven as an output by the MCF5206E or may be driven by the referenced slave device to indicate the completion of the requested data transfer. If the alternate master requested transfer is to a chip select or default memory, the assertion of TA is controlled by the number of wait states and the setting of the Elternate Master Automatic Acknowledge (EMAA) bit in the Chip Select Control Registers (CSCRs) or the Default Memory Control Register (DMCR). If the alternate master requested transfer is a DRAM access, TA is driven by the MCF5206E as an output and asserted at the completion of the transfer.MCF5206E .MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E properly synchronizes the signal. ATA is not used for termination during DRAM accesses.MCF5206E to immediately abort the bus cycle. The assertion of TEA has precedence over the assertion of ATA and TA. NOTE TEA can be asserted .com of one clock after the to a maximum assertion of ATA and still be recognized. TEA has no affect during DRAM accesses.MCF5206E needs use of the bus for one or more bus cycles. BR is negated when the MCF5206E begins an access to the external bus, and remains negated until another internal request occurs with BG negated.MCF5206E can become master of the external bus at the next rising edge of CLK. When the arbiter negates BG, the MCF5206E relinquishes the bus as soon as the current transfer is complete, provided the bus lock bit in the SIMR is not set. If the bus lock bit is set, the MCF5206E will retain bus mastership until the bus lock bit is cleared. The external arbiter must not grant the bus to any other master until the MCF5206E negates BD.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-11MCF5206E asserts this active-low output signal to indicate it has assumed explicit mastership of the external bus. The MCF5206E will assert BD if BG is asserted and either the MCF5206E has a pending bus transfer or the bus lock bit in the SIMR is set to 1. If the MCF5206E is granted mastership of the external bus, but does not have a pending bus transfer and the bus lock bit in the SIMR is cleared, the BD signal is not asserted (implicit mastership of the bus is assumed). If BG is negated to the MCF5206E during a bus transfer and the bus lock bit in the SIMR is cleared, the MCF5206E completes the last transfer of the current access, negate BD, and three-states all bus signals on the rising edge of CLK. If the MCF5206E loses bus ownership during an idle bus period with BD asserted and the bus lock bit in the SIMR cleared, the MCF5206E negates BD and three-states all bus signals on the next rising edge of CLK. If the MCF5206E loses bus ownership during an idle bus period with BD asserted and the bus lock bit in the SIMR set to 1, the MCF5206E continues to assert BD and maintains explicit ownership of the external bus until the bus lock bit in the SIMR is cleared.MCF5206E synchronous clock. CLK clocks or sequences the MCF5206E internal logic and external signals. .comMCF5206E processor to enter reset exception processing. When RSTI is recognized, the address bus, data bus, TT, SIZ, R/W, ATM and TS are three-stated; BR and BD are negated. If RSTI is asserted with HIZ asserted, the MCF5206E enters master reset mode. In this reset mode, the entire MCF5206E (including the DRAM controller refresh circuitry) is reset. You must use master reset for all power-on resets. If RSTI is asserted with HIZ negated, the MCF5206E enters normal reset mode. In this reset mode, the DRAM controller refresh circuitry is not reset and continues to generate refresh cycles at the programmed rate and with the programmed waveform timing.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-15MCF5206E and peripherals with an M-Bus interface (e.g., LED controller, A-to-D converter, D-to-A converter). All devices connected to the M-Bus must have open-drain or open-collector outputs.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E processor status. During debug mode, the timing is synchronous with the processor clock (CLK) and the status is not related to the current bus transfer. Table 2-11 shows the encodings of PST[3:0].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-17MCF5206E processor clock. The internal JTAG controller logic is designed such that holding TCK high or low for an indefinite period of time will not cause the JTAG test logic to lose state information. TCK should be grounded if it is not used.MCF5206E processor. Although this signal is asynchronous, we recommend that TRST make only a 0 to 1 (asserted to negated) transition while TMS is held at a logic 1 value. TRST has an internal pullup so that if it isMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-19MCF5206E is in Debug mode and when MTMOD=0, the MCF5206E is in JTAG mode.MCF5206E enters master reset mode. In this reset mode, the entire MCF5206E (including the DRAM controller refresh circuitry) is reset. You must use master reset for all power-on resets. If RSTI is asserted while HIZ is negated, the MCF5206E enters normal reset mode. In this reset mode, the DRAM controller refresh circuitry is not reset and continues to generate refresh cycles at the programmed rate.MCF5206E signals.MCF5206E Signal SummaryMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Signal Summary (Continued)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 2-21MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-3MCF5206E processor includes a hardware divider which performs a number of integer divide operations. The supported divide functions include: 32/16 producing a 16-bit quotient and 16-bit remainder, 32/32 producing a 32-bit quotient, and 32/32 producing 32-bit remainder.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E does not provide illegal instruction detection on the extension words on any instruction, including MOVEC. If any other nonsupported opcode is executed, the resulting operation is undefined.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-9MCF5206E .MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA 1(0/0) 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 1(0/0) (AX) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(0/1) (AX)+ 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(0/1) -(AX) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(0/1) (D16,AX) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- -- 2(1/1) -- -- (D8,AX,XI) 2(0/1) 2(0/1) 3(1/1) 3(1/1) 3(1/1) -- -- -- -- -- -- -- (XXX).WL 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) -- -- -- -- -- -- --MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-13 RN (AN) 1(0/1) 1(0/1) 1(0/1) -- -- -- -- -- -- -- -- 3(1/0) 3(1/0) 2(1/0) (AN)+ 1(0/1) 1(0/1) 1(0/1) -- -- -- -- -- -- -- -- 3(1/0) 3(1/0) 2(1/0) -(AN) 1(0/1) 1(0/1) 1(0/1) -- -- -- -- -- -- -- -- 3(1/0) 3(1/0) 2(1/0) (D16,AN) 1(0/1) 1(0/1) 1(0/1) -- -- -- -- -- -- -- -- 3(1/0) 3(1/0) 2(1/0) (D8,AN,XN*SF) 2(0/1) 2(0/1) 2(0/1) -- -- -- -- -- -- -- -- 4(1/0) 4(1/0) 3(1/0) XXX.WL 1(0/1) 1(0/1) 1(0/1) -- -- -- -- -- -- -- -- 3(1/0) 3(1/0) 2(1/0) #XXX -- -- -- -- -- -- -- -- -- -- -- 1(0/0) 1(0/0) 1(0/0) Dx Dx Dx Dx Dx Dx Dx Dx 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA RN ,Rx Dy, #imm,Dx #imm, Dy,Dx ,Rx Dy, #imm,Dx ,Dx ,Dx Dy, #imm, Dy, #imm, Dy, #imm, Dy, #imm, ,Rx #imm,Dx ,Dx ,Dx ,Dx ,Dx Dy, #imm,Dx ,Ax ,Dx ,Dx Ry,Rx Ry,Rx Ry,Rx Ry,Rx Ry,Rx,ea,Rw Ry,Rx,ea,Rw Ry,Rx,ea,Rw Ry,Rx,ea,Rw #imm,Dx ,Dx ,Dx ,Dx ,Dx ,Rx Dy, 1(0/0) -- 1(0/0) 1(0/0) 1(0/0) 1(0/0) -- 1(0/0) 1(0/0) 1(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 1(0/0) 1(0/0) 1(0/0) 20(0/0) 20(0/0) 35(0/0) 35(0/0) 1(0/0) 1(0/0) -- 1(0/0) 1(0/0) 1(0/0) 3(0/0) 1(0/0) 3(0/0) -- -- -- -- -- 9(0/0) 9(0/0) 18(0/0) 18(0/0) 1(0/0) -- (AN) 3(1/0) 3(1/1) -- 3(1/1) -- 3(1/0) 3(1/1) -- -- -- 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 3(1/1) 3(1/1) 3(1/0) -- 23(1/0) 23(1/0) 35(1/0) 35(1/0) 3(1/1) -- 1(0/0) -- -- -- -- -- -- 3(1/0) 5(1/0) 3(1/0) 5(1/0) -- 11(1/0) 11(1/0) 20(1/0) 20(1/0) 3(1/0) 3(1/1) (AN)+ -(AN) 3(1/0) 3(1/0) 3(1/1) 3(1/1) -- -- 3(1/1) 3(1/1) -- -- 3(1/0) 3(1/0) 3(1/1) 3(1/1) -- -- -- -- -- -- 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 41/1) 4(1/1) 4(1/1) 4(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/0) 3(1/0) -- -- .com 23(1/0) 23(1/0) 23(1/0) 23(1/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) 3(1/1) 3(1/1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3(1/0) 3(1/0) 5(1/0) 5(1/0) 3(1/0) 3(1/0) 5(1/0) 5(1/0) -- -- 11(1/0) 11(1/0) 11(1/0) 11(1/0) 20(1/0) 20(1/0) 3(1/0) 3(1/1) 20(1/0) 20(1/0) 3(1/0) 3(1/1) (D16,AN) (D16,PC) 3(1/0) 3(1/1) -- 3(1/1) -- 3(1/0) 3(1/1) -- -- -- 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 3(1/1) 3(1/1) 3(1/0) -- 23(1/0) 23(1/0) 35(1/0) 35(1/0) 3(1/1) -- 1(0/0) -- -- -- -- -- -- 3(1/0) 5(1/0) 3(1/0) 5(1/0) -- 11(1/0) 11(1/0) 20(1/0) 20(1/0) 3(1/0) 3(1/1) (D8,AN,XN*SF) (D8,PC,XN*SF) 4(1/0) 4(1/1) -- 4(1/1) -- 4(1/0) 4(1/1) -- -- -- 5(1/1) -- 5(1/1) -- 5(1/1) -- 4(1/1) -- 4(1/0) -- 24(1/0) 24(1/0) XXX.WL 3(1/0) 3(1/1) -- 3(1/1) -- 3(1/0) 3(1/1) -- -- -- 4(1/1) -- 4(1/1) -- 4(1/1) -- 3(1/1) -- 3(1/0) -- 23(1/0) 23(1/0) #XXX 1(0/0) -- -- -- -- 1(0/0) -- -- 1(0/0) 1(0/0) -- -- -- -- -- -- -- 1(0/0) 1(0/0) -- 20(0/0) 20(0/0)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-15,Rx Dy, #imm,Dx #imm, Dy,Dx 1(0/0) 1(0/0) -- 1(0/0) 1(0/0) 1(0/0)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA RN Ay,#imm CCR,Dx ,CCR SR,Dx ,SR 2(0/1) 1(0/0) 1(0/0) 1(0/0) 7(0/0) 9(0/1) -- -- 3(0/0) -- 1(0/0) #imm -- (AN) -- -- -- -- -- -- 1+n(n/0) 1+n(0/n) -- 2(0/1) -- -- (AN)+ -- -- -- -- -- -- -- -- -- -- -- -- -(AN) -- -- -- -- -- -- -- -- -- -- -- -- (D16,AN) -- -- -- -- -- -- 1+n(n/0) 1+n(0/n) -- 2(0/1) 4 -- -- (D8,AN,XN*SF) -- -- -- -- -- -- -- -- -- 3(0/1) 5 -- --,&list MOVEM.L &list, NOP PEA PULSE STOP -- 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) WDEBUG -- 5(2/0) -- -- 5(2/0) -- -- n is the number of registers moved by the MOVEM opcode. 1 indicates that long multiplies have early termination.com cycle count is operand independent after 9 cycles; thus, actual 2If a MOVE.W #imm,SR instruction is executed and imm[13] = 1, the execution time is 1(0/0). 3The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. 4PEA execution times are the same for (d16,PC) 5 PEA execution times are the same for (d8,PC,Xn*SF)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 3-17 RN BSR JMP JSR RTE RTS -- -- -- -- -- (AN) -- 3(0/0) 3(0/1) -- -- (AN)+ -- -- -- 10(2/0) 5(1/0) -(AN) -- -- -- -- -- (D16,AN) (D16,PC) 3(0/1) 3(0/0) 3(0/1) -- -- (D8,AN,XI*SF) (D8,PC,XI*SF) -- 4(0/0) 4(0/1) -- -- MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 4-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-1MCF5206E . 0 = Allow read and write accesses to the SRAM module 1 = Allow only read accesses to the SRAM moduleMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 5-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E bus interface supports synchronous data transfers that can be terminated synchronously or asynchronously and also can be burst or burst-inhibited between the MCF5206E and other devices in the system. This section describes the function of the bus, the signals that control the bus, and the bus cycles provided for data-transfer operations. Operation of the bus is defined for transfers initiated by the MCF5206E as a bus master and for transfers initiated by an external bus master. When the DMA Controller has mastership, it is explicitly stated. The section includes descriptions of the error conditions, bus arbitration, and the reset operation.MCF5206E is the bus master. When an external bus master controls the bus, the address signals are examined when transfer start (TS) is asserted to determine if the MCF5206E should assert chip selects, DRAM control, and/or transfer terminal signals. During an interrupt-acknowledge access, address lines A[27:5] are driven high, A[1:0] are driven low, and A[4:2] indicate the interrupt level being acknowledged.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-1MCF5206E . The output of A[27:24] depends on the setting of PAR[3:0] in the Pin Assignment Register (PAR) in the SIM. Refer to 6.3.2.10 Pin Assignment Register on how to program the Pin Assignment Register (PAR).MCF5206E and all other devices. The data bus can transfer 8, 16, 32, or 128 bits of data per bus transfer. A write cycle drives all 32 bits of the data bus regardless of the port width and operand size.MCF5206E asserts this three-state bidirectional signal for one clock period to indicate the start of each bus cycle. During external master accesses, the MCF5206E monitors transfer start (TS) to detect the start of each external master bus cycle to determine if chip select, DRAM, and/or transfer termination signals should be asserted.MCF5206E monitors this signal to determine if chip selects or DRAM control signals should be asserted.MCF5206E monitors these signals to determine the data size for asserting the appropriate memory control signals. Table 6-1 shows the definitions of the SIZx encoding. Table 6-1. SIZx EncodingMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E does not sample TT[1:0] during external master transfers.MCF5206E does not sample ATM during external master transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-3MCF5206E . NOTE The internal synchronized version of ATA is referred to as "internal asynchronous transfer acknowledge.'' During a read cycle, data is latched on the rising edge of CLK when the internal asynchronous transfer acknowledge is asserted. Consequently, data must remain valid for at least one and a half CLK cycles after the assertion of ATA. Similarly, during a write cycle, data is driven until the falling edge of CLK when the internal asynchronous transfer acknowledge is asserted. ATA must be driven for one and half full clocks to ensure that the MCF5206E properly synchronizes the signal. NOTE For the MCF5206E to accept the transfer as successful with .com an ATA, transfer error acknowledge TEA must be negated until the internal asynchronous transfer acknowledge is asserted or the transfer is completed with a bus error. Asynchronous transfer acknowledge (ATA) is not used for termination during DRAM accesses.MCF5206E -initiated transfers, transfer acknowledge (TA) is an input signal from the referenced slave device indicating completion of the transfer. NOTE For the MCF5206E to accept the transfer as successful with a transfer acknowledge, TEA must be negated throughout the transfer. TA is not used for termination during MCF5206E -initiated DRAM accesses. When an external master is controlling the bus, the MCF5206E can drive TA to indicate the completion of the requested data transfer. If the external master-requested transfer isMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives TA as an output and is asserted at the completion of the transfer.MCF5206E experiences a double bus fault, it enters the halted state. To exit the halt state, reset the MCF5206E .MCF5206E uses the address bus (A[27:0]) to specify the location for a data transfer and the data bus (D[31:0]) to transfer the data. Control and attribute signals indicate the beginning and type of a bus cycle as well as the address space, direction, and size of the transfer. The selected device or the number of wait states programmed in the memory control register (the Chip Select Control Register (CSCR), the DRAM Controller Control Registers (DCCR, including the DRAM Controller Timing Register (DCTR)), or the Default Memory Control Register (DMCR)) control the length of the cycle. The MCF5206E clock is distributed internally to provide logic timing. All bus signals are synchronous with the rising edge of CLK with the exception of row address strobes (RAS[1:0]) and column address strobes (CAS[3:0]), which can be asserted and negated synchronous with the falling edge of CLK. Inputs to the MCF5206E (other than the interrupt priority level signals (IPLx), reset in (RSTI) and ATA signals) are synchronously sampled and must be stable during the sample window defined by tsi and thi (as shown in Figure 6-1) to guarantee proper operation. The asynchronous IPLx, RSTI and ATA signals are internally synchronized to resolve the input to a valid level before being used.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-5MCF5206E begin to transition on the rising CLK edges, with the exception of RAS[1:0] and CAS[3:0], which begin to transition on the falling CLK edges. Specifically, RAS[1:0] is asserted and negated synchronous with the falling edge of CLK, while CAS[3:0] is asserted synchronous with the falling edge of CLK and can be negated synchronous with either the falling edge or the rising edge of CLK. During external master accesses where the MCF5206E drives TA as an output, TA is always driven negated for one clock cycle before being placed in a high-impedence state.MCF5206E supports byte, word, and longword operands and allows accesses to 8-, 16-, and 32-bit data ports. With the MCF5206E , you can select the port size of the specific memory, enable internal generation of transfer termination, and set the number of wait states for the external slave being accessed by programming the Chip Select Control Registers (CSCRs), the DRAM Controller Control Registers (DCCRs), and the Default Memory Control Register (DMCR). For more information on programming these registers, refer to the SIM, Chip Select, and DRAM Controller sections. NOTE The MCF5206E compares the address for the current bus transfer with the address and mask bits in the Chip SelectMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E compares the address and mask in chip select 0 - 7 control registers (chip select 0 is compared first), then the address and mask in DRAM bank 0 - 1 control LOWEST PRIORITY registers. If the address does not match in either or these, the MCF5206E uses the control bits in the Default Memory Control Register (DMCR) to control the bus transfer. If the Default Memory Control Register (DMCR) control bits are used, no chip select or DRAM .com control signals are asserted during the transfer.MCF5206E reads the port size for each transfer from either the Chip Select Control Registers (CSCRs), the DRAM Controller Control Registers (DCCRs), or the Default Memory Control Register (DMCR) at the start of each bus cycle. This allows the MCF5206E to transfer operands from 8-, 16-, or 32-bit ports. The size of the transfer is adjusted to accommodate the port size indicated. A 32-bit port must reside on data bus bits D[31:0], a 16-bit port must reside on data bus bits D[31:16], and an 8-bit port must reside on data bus bits D[31:24]. This requirement ensures that the MCF5206E correctly transfers valid data to 8-, 16-, and 32-bit ports. The bytes of operands are designated as shown in Figure 6-2. The most significant byte of a longword operand is OP0; OP3 is the least significant byte. The two bytes of a word length operand are OP2 (most significant) and OP3. The single byte of a byte length operand is OP3. These designations are used in the figures and descriptions that follow.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-7MCF5206E for 8-, 16-, and 32 bit devices. The four bytes shown are connected through the internal data bus and data multiplexer to the external data bus. This path is how the MCF5206E supports programmable port sizing and operand misalignment. The data multiplexer establishes the necessary connections for different combinations of address and data sizes.MCF5206E MCF5206E Interface to Various Port Sizes The multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For example, OP3 can be routed to D[7:0], as would be the normal case when interfacing to a 32-bit port. OP3 can be routed to D[23:16] for interfacing to a 16-bit port, or it can be routed to D[31:24] for interfacing to an 8-bit port. The operand size, address, and port size of the memory being accessed determines the positioning of bytes.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E can burst anytime the port size of the external slave being accessed is smaller than the operand size. If bursting is enabled, the MCF5206E performs burst transfers depending on the port size and operand alignment. For any transfer, the number of bytes transferred during a bus cycle is equal to or less than the size indicated by the SIZx outputs. For example, during the first bus cycle of a longword transfer to a 16-bit port where bursting is enabled, the SIZx outputs remains constant throughout the transfer and indicates that four bytes are to be transferred, although only two bytes are moved at a time.Table 6-5 lists the encodings for the SIZx bits for each port size for transfers where bursting is both enabled and disabled. Table 6-5. SIZx Encoding for Burst- and Bursting-Inhibited PortsMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLEMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-11MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type. Access type and mode (ATM) identifies the transfer as reading code. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven low to indicate a longword transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates transfer start (TS), drives access type and mode (ATM) high to identify the transfer as supervisor. The selected device(s) places the addressed data onto D[31:0] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:0]. If TA is asserted, the transfer of the longword is complete and the transfer terminates. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted. If the bus monitor timer is enabled andMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E to the external data bus. For example, if a longword transfer is generated to a 16-bit port, the MCF5206E starts the cycle with A[1:0] set to $0 and read the first word. The MCF5206E then increments A[1:0] to $2 and reads the second word. The data for both word reads is sampled from DATA[31:16]. Bytes labeled X are "don't cares." Table 6-8. Internal to External Data Bus Multiplexer - Write CycleMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-13MCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO WRITE (R/W = 0) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE SYSTEMMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type. Access type and mode (ATM) identifies the transfer as writing data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates transfer start (TS), drives ATM high to identify the transfer as supervisor, and places the data on the data bus (D[31:0]). The selected device(s) asserts the transfer acknowledge (TA) if it is ready to latch the data. At the end of C2, the selected device latches the current value of D[31:16], and the MCF5206E samples the level of TA. If TA is asserted, the transfer of the word is complete and the transfer terminates. If TA is negated, the MCF5206E continues to output the data and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-15MCF5206E performs word, longword, and line transfers in burst mode. When burst mode is selected, the size of the transfer (indicated by SIZ[1:0]) reflects the size of the operand being read, not the size of the port being accessed (i.e., a line transfer is indicated by SIZ[1:0] = $3 and a longword transfer is indicated by SIZ[1:0] = $0, regardless of the size of the port or the number of transfers required to access the entire set of data). The MCF5206E supports burst-inhibited transfers for memory devices that cannot support bursting. For this type of bus cycle, you should clear the burst-enable bit in the Chip Select Control Registers (CSCRs) or Default Memory Control Register (DMCR). NOTE No burst-enable bit is provided for DRAM accesses. DRAM transfers are always bursted if the operand size is larger than the port size. The MCF5206E uses line read transfers to access 16 Bytes to support cache line filling and for a MOVEM instruction, when appropriate. A line read accesses a block of four longwords, aligned to a longword memory boundary, by supplying a starting address that .com points to one of the longwords and incrementing A3, A2, A1, and A0 of the supplied address for each transfer. A longword read accesses a single longword aligned to a longword boundary and increments A1 and A0 if the accessed port size is smaller than 32 bits. A word read accesses a single word of data, aligned to a word boundary and increments A0 if the accessed port size is smaller than 16 bits. Figure 6-8 is a flowchart for bursting read transfers to 8-, 16-, or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the transfer, and the specific number of cycles needed for each transfer. A bursted read transfer can be from two to sixteen transfers long. The flowchart shown in Figure 6-8 is for a bursting transfer of four transfers long.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLEMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-17MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type. Access transfer and mode (ATM) identifies the transfer as reading code. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS, drives ATM low to identify the transfer as user. The selected device(s) places the first byte of the addressed data on to D[31:24] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the first byte of the word read is complete. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E increments A0 to address the next byte of the word transfer. The selected device(s) places the second byte of the addressed data onto D[31:24] and asserts the transfer acknowledge (TA). At the end of C3, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the word read is complete and the transfer is terminated. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted.MCF5206E uses line-write transfers to access a 16-byte operand for a MOVEM instruction, when appropriate. A line write accesses a block of four longwords, aligned to a longword memory boundary, by supplying a starting address that points to one of the longwords and increments A[3], A[2], A[1], and A[0] of the supplied address for each transfer. A longword write accesses a single longword aligned to a longword boundary and increments A[1] and A[0] if the accessed port size is smaller than 32 bits. A word write accesses a single word of data, aligned to a word boundary and increments A0 if the accessed port size is smaller than 16 bits. Table 6-9 lists the encodings for the SIZx bits for each port size for transfers where bursting is both enabled and disabled. Table 6-9. SIZx Encoding for Burst- and Bursting-Inhibited PortsMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-19MCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO WRITE (R/W = 0) DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLEMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type. Access type and mode (ATM) identifies the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $3 to indicate a line transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS, drives ATM low to identify the transfer as user, and places the data on the data bus (D[31:0]). The selected device(s) asserts the transfer acknowledge (TA) if it is ready to latch the data. At the end of C2, the selected device latches the current value of D[31:0], and the MCF5206E samples the level of TA. If TA is asserted, the transfer of the first longword is complete. If TA is negated, the MCF5206E MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-21MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted. Clock 3 (C3) The MCF5206E increments A[3:2] to address the next longword of the line transfer and drives D[31:0] with the second longword of data. The selected device(s) asserts the TA if it is ready to latch the data. At the end of C3, the MCF5206E samples the level of TA and if TA is asserted, the second longword transfer of the line write is complete. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted.MCF5206E three-states D[31:0] at the start of the next CLK cycle.MCF5206E performs word, longword, and line transfers in burst-inhibited mode. When burst-inhibit mode is selected, the size of the transfer (indicated by SIZ[1:0]) reflects the port size if the operand being read is larger than the port size or the operand size if the port size is larger than the operand size. A transfer size of line (SIZ[1:0] = $3) is never indicated in burst-inhibited mode. If the operand size is line, the size pins (SIZ[1:0]) always indicate the port size. Refer to Table 6-9 for SIZx encodings for each port size for burst-inhibited transfers. NOTE All transfers to DRAM that have an operand size larger than the port size are bursted. Burst-inhibited transfers cannot be generated for DRAM accesses.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-23MCF5206E 1. 2. 3. 4. 5. 1. 2. 1. 2. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE NEGATE TS DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE REGISTER DATA RECOGNIZE THE 1ST TRANSFER IS DONE INCREMENT APPROPRIATE ADDRESS BITS BASED ON A[3:0] AND PORT SIZE DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE NEGATE TS ASSERT ATM TO INDICATE APPROPRIATE ACCESS TYPE REGISTER DATA RECOGNIZE THE 2ND TRANSFER IS DONE 1. 2. 3. 1. 2. 3.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and drives ATM high to identify the transfer as code. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS and drives ATM high to identify the transfer as supervisor. The selected device(s) places the first byte of the addressed data onto D[31:24] and asserts TA. At the end of C2, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the first byte of the longword read is complete. If TA is negated, the MCF5206E continues toMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-25MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted. Clock 3 (C3) The MCF5206E increments A[1:0] to address the second byte of the longword transfer. The MCF5206E continues to drive transfer type (TT[1:0]), read/write (R/W) and size (SIZ[1:0]) signals to indicate a byte read. Access transfer mode (ATM) is driven high to indicate the transfer as code. The MCF5206E asserts TS to indicate the beginning of the second transfer of the bus cycle. Clock 4 (C4)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO WRITE (R/W = 0) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE SYSTEMMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-27MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS, drives ATM high to identify the transfer as supervisor and places the data on the data bus (D[31:0]). The selected device(s) asserts TA if it is ready to latch the data. At the end of C2, the selected device latches the current value of D[31:16], and the MCF5206E samples the level of TA. If TA is asserted, the transfer of the first word is complete. If TA is negated, the MCF5206E continues to outputMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E continues to sample TA on successive rising edges of CLK until it is asserted. Clock 3 (C3) The MCF5206E increments A[1:0] to address the next word, asserts TS and drives ATM low to identify the transfer as code or data. Clock 4 (C4) This clock is identical to C2 except that the data driven corresponds to the second word of data. This is the last CLK cycle of the longword-write transfer and the MCF5206E threestates D[31:0] at the start of the next CLK cycle.MCF5206E provides an asynchronous acknowledge that can be used for termination of all MCF5206E transfers except accesses to DRAM. ATA is synchronized internally before being used. If recognition by a specific CLK rising edge is required, ATA must meet the specified setup and hold times to CLK. Because of the internal synchronization of ATA, data must be driven on the bus until the asynchronous transfer acknowledge is recognized internally. If transfer error acknowledge (TEA) is asserted while ATA is being synchronized internally, the transfer terminates in an error. NOTE .com The internal synchronized version of (ATA) is referred to as ``internal asynchronous transfer acknowledge.'' Because of the time required to internally synchronize ATA during a read cycle, data is latched on the rising edge of CLK when the internal asynchronous transfer acknowledge is asserted. Consequently, data must remain valid for at least one and half CLK cycles after the assertion of ATA. Similarly, during a write cycle, data is driven until the falling edge of CLK when the internal asynchronous transfer acknowledge is asserted. Figure 6-16 is a flowchart for read transfers to 8-, 16-, or 32-bit ports with asynchronous termination. Bus operations are similar for each case and vary only with the size indicated,MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-29MCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE SYSTEMMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as code. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS and drives ATM low to identify the transfer as user. The selected device(s) asserts ATA with the required setup time prior to the falling clock edge.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-31MCF5206E samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:24]. If internal asynchronous transfer acknowledge is asserted, the byte transfer is complete and the transfer terminates. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling edge of C2, internal asynchronous transfer acknowledge is asserted by the rising edge of C3.MCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO WRITE (R/W = 0) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE .com ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE SYSTEMMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS, drives ATM low to identify the transfer as user and places the data on the data bus (D[31:0]). The selected slave device asserts ATA prior to the falling edge of the clock. The selected slave device may latch the data present on the data bus or may wait until the end of Clock 3 (after internal asynchronous transfer acknowledge has been asserted).MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-33MCF5206E samples the level of internal asynchronous transfer acknowledge and if it is asserted, the transfer of the byte is complete and the transfer terminates. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling edge of C2 meeting the setup time requirement, internal asynchronous transfer acknowledge is asserted by the rising edge of C3.MCF5206E performs word, longword, and line transfers in burst mode. When burst mode is selected and the transfer is not to DRAM, the transfer can be terminated synchronously using TA, or asynchronously using ATA. The transfer attributes are the same for both the synchronous and asynchronously terminated burst transfers. Figure 6-20 is a flowchart for bursting read transfers to 8-, 16-, or 32-bit ports using asynchronous termination. Bus operations are similar for each case and vary only with the .com size indicated, the portion of the data bus needed for the transfer, and the specific number of cycles used for each transfer. A bursted transfer can be from two to 16 transfers long.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE SYSTEMMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-35MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as reading data. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate a longword transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates TS, drives ATM high to identify the transfer as supervisor. The selected device(s) asserts ATA prior to the falling edge of the clock. Clock 3 (C3) At the end of C3, the MCF5206E samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:16]. If internal asynchronous transfer acknowledge is asserted, the transfer of the first word is complete. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling edge of C2, internal asynchronous transfer acknowledge is asserted by the rising edge of C3. Clock 4 (C4) The MCF5206E increments A[1:0] to address the next word. The selected device(s) asserts ATA prior to the falling edge of the clock. Clock 5 (C5)MCF5206E samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:16]. If internal asynchronous transfer acknowledge is asserted, the transfer of the second word is complete and the transfer is terminated. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling edge of C4, internal asynchronous transfer acknowledge is asserted by the rising edge of C5.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-37MCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO WRITE (R/W = 0) DRIVE SIZ[1:0] TO INDICATE WORD, LONGWORD OR LINE DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLEMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $3 to indicate a line transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-39MCF5206E negates TS, drives ATM low to identify the transfer as user and places the data on the data bus (D[31:0]). The selected device(s) asserts ATA if it is ready to latch the data, which is recognized by the MCF5206E on the next falling clock edge. Clock 3 (C3) If the selected device asserted asynchronous transfer acknowledge during C2, the selected device must latch the data by the end of C3. At the end of C3, the MCF5206E samples the level of internal asynchronous transfer acknowledge. If internal asynchronous transfer acknowledge is asserted, the transfer of the first longword is complete. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling edge of C2, the internal asynchronous transfer acknowledge is asserted by the rising edge of C3. Clock 4 (C4) The MCF5206E increments A[3:2] to address the next longword of the line transfer and drives D[31:0] with the second longword of data. The selected device(s) asserts ATA if it is ready to latch the data. At the end of C4, the MCF5206E samples the level of internal .com ATA and if it is asserted, the second longword transfer of the line write is complete. If internal ATA is negated, the MCF5206E continues to sample internal ATA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal ATA on successive falling edges of the CLK until it is asserted. Clock 5 (C5) This clock is identical to C3 except that the data value corresponds to the second longword of data for the burst. Clock 6 (C6) This clock is identical to C4 except that once internal ATA is asserted, the address and the data values correspond to the third longword of data for the burst. Clock 7 (C7) This clock is identical to C3 except that the data value corresponds to the third longword of data for the burst. Clock 8 (C8) This clock is identical to C4 except that once internal ATA is asserted the address and data value correspond to the fourth longword of data for the burst.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E three-states D[31:0] at the start of the next CLK cycle.MCF5206E performs word, longword, and line transfers in burst-inhibited mode. When burst-inhibit mode is selected, the size of the transfer (indicated by SIZ[1:0]) reflects the port size if the operand being read is larger than the port size, or the operand size if the port size is larger than the operand size. A transfer size of line (SIZ[1:0] = $3) is never indicated in burst-inhibited mode. If the operand size is line, the size pins (SIZ[1:0]) always indicates the port size. The basic transfer of a burst-inhibited read using asynchronous termination is the same as "normal" read using asynchronous termination with the addition of more transfers, until the entire operand has been accessed. Figure 6-24 is a flowchart for burst-inhibited read transfers to 8-, 16-, or 32-bit ports with asynchronous termination. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the transfer, and the specific number of cycles needed for each transfer. The flowchart .com is specifically for a burst-inhibited transfer of four transfers long.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-41MCF5206E 1. 2. 3. 4. 5. DRIVE ADDRESS ON A[27:0] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE ACCESS TYPE ASSERT TS FOR ONE CLK CYCLE 1. 2. 3.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as code. The read/write (R/W) signal is driven high for a read cycle and the size signals (SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS, drives ATM low to identify the transfer as user. The selected device(s) asserts ATA, which is recognized at the next falling clock edge.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-43MCF5206E samples the level of internal asynchronous transfer acknowledge and if it is asserted, latches the current value of D[31:24]. If internal asynchronous transfer acknowledge is asserted, the transfer of the first byte is complete. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling edge of C2, internal asynchronous transfer acknowledge is asserted by the rising edge of C3.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-45MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates TS, drives ATM high to identify the transfer as supervisor and drives the data on the data bus (D[31:0]). The selected device(s) asserts ATA if it is ready to latch the data. Clock 3 (C3) At the end of C3, the MCF5206E samples the level of internal asynchronous transfer acknowledge and if it is asserted, terminates the first word transfer. If internal asynchronous transfer acknowledge is asserted, the transfer of the first word is complete. If internal asynchronous transfer acknowledge is negated, the MCF5206E continues to sample internal asynchronous transfer acknowledge and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample internal asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted by the falling edge of C2, the rising edge of C3 asserts the internal asynchronous transfer acknowledge. Clock 4 (C4) This clock is identical to C1 except the MCF5206E increments the address to indicate the next word. Clock 5 (C5)MCF5206E three-states the data bus after the next rising edge of CLK.MCF5206E is in a system with multiple masters and you require zero wait-state operation, you can tie ATA to GND to achieve zero wait-state operation for nonDRAM transfers. ATA must be used in this case as the MCF5206E can drive TA during external master accesses. When ATA is tied to GND, all nonDRAM transfers follow the timing shown with TA asserted with zero wait states. If the MCF5206E is the only master in the system, TA and BG can be tied to GND to grant mastership of the external bus to the MCF5206E and achieve zero wait-state operation.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-47MCF5206E is not the only bus master in the system. Damage to the part could occur if TA is tied to GND and external master accesses using 5206e generated termination.MCF5206E data formats can be located in memory on any byte boundary. A byte operand is properly aligned at any address; a word operand is misaligned at an odd address; and a longword is misaligned at an address that is not evenly divisible by four. However, because operands can reside at any byte boundary, they can be misaligned. Although the MCF5206E does not enforce any alignment restrictions for data operands (including program counter (PC) relative data addressing), some performance degradation occurs when additional bus cycles are required for longword or word operands that are misaligned. For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. An address error exception occurs with any attempt to prefetch an instruction word at an odd address. The MCF5206E converts misaligned operand accesses that are noncacheable to a sequence of aligned accesses. Figure 6-28 illustrates the transfer of a longword operand from a byte address to a 32-bit port, requiring more than one bus cycle. In this example, .com the SIZ[1:0] signals specify a byte transfer, and the byte offset of $1. The slave device supplies the byte and acknowledges the data transfer. When the MCF5206E starts the second cycle, the SIZ[1:0] signals specify a word transfer with a byte offset of $2. The next two bytes are transferred during this cycle. The MCF5206E then initiates the third cycle, with the SIZ[1:0] signals indicating a byte transfer. The byte offset is now $0; the port supplies the final byte and the operation is complete. Figure 6-29 is similar to the example illustrated in Figure 6-28 except that the operand is word-sized and the transfer requires only two bus cycles.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E chip selects, DRAM, and default memory control signals must initiate aligned transfers only.MCF5206E or is ready to send information that the ColdFire core requires, it can signal the ColdFire core to take an interrupt exception. The interrupt exception transfers control to a routine that responds appropriately. The peripheral device uses the interrupt priority level/interrupt request signals (IPLx/IRQx) to signal an interrupt condition to the MCF5206E .MCF5206E has two levels of interrupt masking. The first level of interrupt masking is in the interrupt controller in the System Integration Module (SIM) which masks individual interrupt inputs and then outputs the interrupt priority level of the highest pending unmasked interrupt to the ColdFire core. The Status Register (SR) provides the second level of interrupt masking in the ColdFire core. The value of the SR interrupt mask is the highest priority level that the ColdFire core ignores. When an interrupt request has a priority higher than the value in the mask, the ColdFire core makes the request a pending interrupt. For more information about the Status Register refer to Section 3.2.2.1 Status Register in the ColdFire Core Section.MCF5206E continuously samples the external interrupt input signals and synchronizes and debounces these signals. An interrupt request must be held constant for at least two consecutive CLK periods to be considered a valid input. If the external interrupt inputs are programmed to individual interrupt requests (at level 1, 4, and 7), the interrupt request must maintain the interrupt request level until the MCF5206E acknowledges the interrupt to guarantee that the interrupt is recognized. If the external interrupt inputs are programmed to be interrupt priority levels, the interrupt request must maintain the interrupt request level or a higher priority level until the MCF5206E acknowledges the interrupt to guarantee that the interrupt is recognized.MCF5206E takes an interrupt exception for a pending interrupt within one instruction boundary after processing any other pending exception with a higher priority. Thus, the MCF5206E executes at least one instruction in an interrupt exception handler before recognizing another interrupt request. If the AVEC bit in the Interrupt Control Register (ICR) for the interrupt being acknowledged is set to 1 (enabling autovectoring), the interrupt acknowledge vector is generated internally and no interrupt acknowledge cycle is generated on the external bus. Refer to the SIM section 7.3.2.3 Interrupt Control Register for ICR programming.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-49MCF5206E processes an interrupt exception, it performs an interrupt acknowledge bus cycle to obtain the vector number that contains the starting location of the interrupt exception handler.MCF5206E 1. 2. 3. 4. 5. 6. 7. DRIVE $7FFFFF ON A[27:5] DRIVE $0 ON A[1:0] DRIVE INTERRUPT LEVEL ON A[4:2] DRIVE R/W TO READ (R/W = 1) DRIVE SIZ[1:0] TO INDICATE BYTE (SIZ1 = $0, SIZ0 =$1) DRIVE TT[1:0] AND ATM TO INDICATE INTERRUPT ACKNOWLEDGE (TT[1] = TT[0] = $1 AND ATM = $1) ASSERT TS FOR ONE CLK CYCLE SYSTEMMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The address bus is driven with $7FFFFF on A[27:5], $0 on A[1:0] and the interrupt level being acknowledged on A[4:2]. The transfer type (TT[1:0]) signals are driven to $3 and the ATM is driven high to identify the access as an interrupt acknowledge cycle. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206E asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates transfer start (TS), drives access type and mode (ATM) low to identify the transfer as an interrupt acknowledge cycle. The selectedMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-51MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:24] which contains the interrupt vector number. If TA is asserted, the transfer of the interrupt vector is complete and the transfer terminates. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edges of CLK until it is asserted. NOTE Interrupt acknowledge cycles can be asynchronously acknowledged using ATA. As long as ATA is asserted by the falling edge of C2, internal asynchronous transfer acknowledge is asserted by the rising edge of C3. The interrupt vector must remain driven on D[31:24] until internal asynchronous transfer acknowledge is asserted.MCF5206E recognizes a bus error condition for an access, the access is .com terminated immediately. An access that requires more than one transfer, aborts without completing the remaining transfers if TEA is asserted, regardless of whether the access uses burst or burst-inhibited transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and ATM identifies the transfer as code. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate a longword transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) During C2, the MCF5206E negates TS, drives ATM high to identify the transfer as supervisor. The selected device detects an error and asserts TEA. At the end of C2, the MCF5206E samples the level of TEA. If it is asserted, the transfer of the longword is aborted and the transfer terminates.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-53MCF5206E to accept the transfer as successful with an ATA, TEA must be negated until the internal asynchronous transfer acknowledge is asserted or the transfer is completed with a bus error.MCF5206E bus protocol provides for one bus master at a time: either the MCF5206E or an external device. If more than one external bus master is connected to the bus, an external arbiter can prioritize requests and determine which device is granted access to the bus. Bus arbitration is the protocol by which the MCF5206E or an external device becomes the bus master. When the MCF5206E is the bus master, it uses the bus to read instructions and transfer data not contained in its internal cache or memory to and from external memory. When an external bus master owns the bus, the MCF5206E can monitor the external bus master's transfers and assert chip select and DRAM control, and transfer termination signals. This capability is discussed in more detail in Section 6.10 External Bus Master Operation.MCF5206E bus arbitration can be used in two modes. A two-wire mode is provided for systems where the MCF5206E and a single external bus master are the only two masters arbitrating for use of the external bus. This arbitration mode uses the bus grant (BG) and bus driven (BD) signals. The bus request (BR) signal can be ignored by the external bus master. The second mode is provided for systems where multiple external bus masters are arbitrating for use of the external bus. This arbitration mode requires an external bus arbiter and uses the bus grant (BG), bus driven (BD) and bus request (BR) signals to control usage of the external bus. In either arbitration mode, the bus arbitration unit in the MCF5206E operates synchronously and transitions between states on the rising edge of CLK. For systems where the MCF5206E is the only possible bus master, the bus can be continuously granted to the MCF5206E by tying bus grant (BG) to GND. An arbiter is not required.MCF5206E to share the external bus with a single external bus master without requiring an external bus arbiter. Figure 6-33 is a block diagram showing the MCF5206E connecting to an external bus master using theMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E is connected to the active-high HOLDREQ output of the external bus master and the activelow bus-driven (BD) output of the MCF5206E is connected to the active-high HOLDACK input of the external bus master. Because the external bus master controls the assertion/ negation of HOLDREQ, it controls when the MCF5206E is granted the bus, making the MCF5206E the lower priority master. You can program the bus lock (BL) bit in the SIM Configuration Register (SIMR) to a 1, instructing the MCF5206E to retain control of the external bus, even when bus grant (BG) is negated. This lets you control the priority of the MCF5206E with respect to the external master when in two-wire mode.MCF5206E TO/FROM EXTERNAL MEMORY AND CONTROLMCF5206E Two-Wire Mode Bus Arbitration Interface When the external master is not using the bus, it negates HOLDREQ driving bus grant (BG) low, granting the bus to the MCF5206E . When the MCF5206E has an internal bus request pending and bus grant (BG) is low, the MCF5206E drives BD low, negating HOLDACK to the external bus master. When the external bus master requires use of the external bus, it asserts HOLDREQ, driving bus grant (BG) high, requesting the MCF5206E to relinquish the bus. If bus grant (BG) is negated while a bus cycle is in progress and if the bus lock bit is cleared, the MCF5206E relinquishes the bus at the completion of the bus cycle. Note that the MCF5206E considers the individual transfers of a burst or burstinhibited access to be a single bus cycle and does not relinquish the bus until the completion of the last transfer of the series. When the bus has been granted to the MCF5206E , one of two situations can occur. In the first case, the MCF5206E has an internal bus request pending, the MCF5206E asserts BD to indicate explicit bus ownership and begins the pending bus cycle by asserting TS. TheMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-55MCF5206E continues to assert BD until the completion of the bus cycle. If bus grant (BG) is negated by the end of the bus cycle and the Bus Lock bit in the SIMR is 0, the MCF5206E negates BD. As long as bus grant (BG) is asserted, BD remains asserted to indicate the bus is owned by the MCF5206E and the MCF5206E continuously drives the address bus, attributes and control signals. In the second situation, the bus is granted to the MCF5206E , but the MCF5206E does not have an internal bus request pending and the Bus Lock bit in the SIMR is 0, so it takes implicit ownership of the bus. Implicit ownership of the bus occurs when the MCF5206E is granted the bus, but there are no pending bus cycles and the bus lock bit (BL) in the SIMR is set to 0. The MCF5206E does not drive the bus and does not assert bus driven BD if the bus is implicitly owned. If an internal bus request is generated or the bus lock bit in the SIM Configuration Register (SIMR) is set to 1, the MCF5206E assumes explicit ownership of the bus. If explicit ownership was assumed because of an internal request being generated, the MCF5206E immediately begins an access and simultaneously asserts bus driven BD and TS. If explicit ownership was assumed because of the bus lock bit being set to 1, the MCF5206E asserts bus driven BD and drives the address, attributes and control signals but does no assert TS and does not begin a bus transfer. In the case where the bus lock bit is set to 1, the MCF5206E is the explicit master of the external bus, but does not begin an access until an internal request is generated. Figure 6-34 illustrates implicit and explicit bus ownership because of the bus lock bit being setMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E MCF5206E . During Clock 4 (C4) and Clock 5 (C5) the MCF5206E is implicit owner because an internal access is not pending and the bus lock bit is cleared. In C5, the bus lock bit is set to 1, causing the MCF5206E to take explicit ownership of the bus in Clock 6 (C6) by asserting BD. In Clock 7 (C7) the external master removes the bus grant to the MCF5206E . Because the bus lock bit is set to 1, the MCF5206E does not relinquish the bus (the MCF5206E continues to assert BD). NOTE The MCF5206E can start a transfer during the CLK cycle after BG is asserted. The external master should not assert BG to the MCF5206E until it has stopped driving the bus. BG cannot be asserted while the external master transfer is still in progress or damage to the part could occur.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-57MCF5206E , one of two situations can occur. In the first case, the bus lock bit in the SIM Configuration Register (SIMR) is cleared and the MCF5206E has implicit ownership of the bus. When the external bus master negates BG, the MCF5206E negates BD and three-state the address, data, TS, R/W, and SIZ signals after completing the current bus cycle. Figure 6-35 illustrates two-wire bus arbitration with the bus lock bit cleared.MCF5206E MCF5206E . At this point, the bus lock bit is cleared, but because there is an internal access pending, the MCF5206E asserts BD during C4 and begins the access. Thus, the MCF5206E becomes the explicit master of the external bus. This access is a burst-inhibited access. During C5, the external master removes the grant from the MCF5206E by negating BG. Because the MCF5206E is performing a burst-inhibited access, it continues to assert BD until the final transfer of the access has completed. The MCF5206E negates BD during C8, returning ownership of the external bus to the external master. In the second case, the bus lock bit in the SIM Configuration Register (SIMR) is set to 1 and the MCF5206E has explicit ownership of the bus. In this case, when the external bus master negates BG, the MCF5206E continues to assert BD and continues to drive address, attributes, and control signals. The MCF5206E retains mastership of the bus until the bus lock bit in the SIM Configuration Register (SIMR) is cleared. By setting the bus lock bit to 1, you can select the MCF5206E to be the highest priority master, even whenMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E can be guaranteed mastership of the bus when executing time critical, bus intensive operations. Figure 6-36 illustrates bus arbitration using the bus lock bit to control the arbitration.MCF5206E EXTERNAL MASTERMCF5206E . At this point the bus lock bit is set to 1, and there is an internal access pending so the MCF5206E asserts bus driven (BD) during C4 and begins the access. Thus, the MCF5206E becomes the explicit master of the external bus. Also during C4, the external master removes the grant from the MCF5206E by negating bus grant (BG). Because the MCF5206E is the current bus master and the bus lock bit in the SIM Configuration Register (SIMR) is set to 1, it continues to assert BD even after the current transfer has completed. The MCF5206E negates the bus lock bit in SIMR during C8. Because bus grant (BG) is negated, the MCF5206E negates bus driven (BD) during C9 and three-states the external bus, thereby passing ownership of the external bus back to the external master. Figure 6-37 is a bus arbitration state diagram for the MCF5206E bus arbitration protocol. Table 6-10 lists the conditions that cause bus arbitration state changes. Table 6-11 describes the MCF5206E bus ownership, bus driving and assertion of bus driven (BD) forMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-59MCF5206E Two-Wire Bus Arbitration Protocol State Diagram Table 6-10. MCF5206E Two-Wire Bus Arbitration Protocol Transition ConditionsMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Two-Wire Arbitration Protocol State DiagramMCF5206E can be in any one of four arbitration states during bus operation: reset, external master ownership, implicit ownership, and explicit ownership. The MCF5206E enters the reset state whenever RSTI or software watchdog reset is asserted in any bus arbitration state. When RSTI and the software watchdog reset are negated, the MCF5206E proceeds to the implicit ownership state or external master ownership state, depending on BG. The external master ownership state denotes the MCF5206E does not have ownership (BG negated) of the bus and the MCF5206E does not drive the bus. The MCF5206E can assert memory control signals (i.e., CS[7:0], WE[3:0], RAS[1:0] or CAS[3:0]) and transfer acknowledge (TA) during this state.MCF5206E owns the bus because BG is asserted to it. The MCF5206E , however, is not ready to begin a bus cycle and the bus lock bit in the SIM Configuration Register (SIMR) is cleared. In this case, the MCF5206E keeps the bus three-stated until an internal bus request occurs or the bus lock bit in the SIMR is set to 1. The MCF5206E explicitly owns the bus when the bus is granted to it (BG asserted) and at least one bus cycle has been initiated or the bus lock bit in the SIMR is set to 1. The MCF5206E asserts BD in this state to indicate the MCF5206E has explicit ownership of the bus. Until BG is negated, the MCF5206E retains explicit ownership of the bus whether or not active bus cycles are being executed. Once BG is negated and the bus lock bit in the SIMR is cleared, the MCF5206E relinquishes the bus at the end of the current bus cycle. When the MCF5206E is ready to relinquish the bus, it negates BD and three-states the bus signals.MCF5206E to share the external bus with any number of external bus masters. In this mode, an external arbiter must be provided to assign priorities to each of the possible bus masters and determine which master should be allowed use of the external bus. The bus arbitration signals of theMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-61MCF5206E , BR, BD, and BG connect to the bus arbiter, allowing the bus arbiter to control use of the external bus by the MCF5206E . The MCF5206E requests the bus from the external bus arbiter by asserting bus request (BR) whenever an internal bus request is pending (the ColdFire core requests an access). The MCF5206E continues to assert BR until after the start of the external bus transfer. The MCF5206E can negate BR at any time regardless of the bus grant (BG) status. If the bus is granted to the MCF5206E when an internal bus request is generated, the MCF5206E asserts bus driven (BD) simultaneously with transfer start, allowing the access to begin immediately. The MCF5206E always drives BR and BD. They cannot be directly wireORed with other devices.MCF5206E that it has been granted the bus and may begin a bus cycle after the rising edge of the next CLK. If BG is negated while a bus cycle is in progress, the MCF5206E relinquishes the bus at the completion of the bus cycle, except if the bus lock (BL) bit in the SIMR is set. To guarantee that the bus is relinquished, BL must be cleared and BG must be negated prior to the rising edge of the CLK in which the last TA, TEA or internal asynchronous transfer acknowledge is asserted. Note that the MCF5206E considers any series of bus transfers of a burst or a burstinhibited transfer to be a single bus cycle and does not relinquish the bus until completion of the last transfer of the series. When the bus has been granted to the MCF5206E in response to the assertion of BR, one of two situations can occur. In the first case, the MCF5206E has an internal bus request .com pending, the MCF5206E asserts BD to indicate explicit bus ownership and begins the pending bus cycle by asserting TS. The MCF5206E continues to assert BD until the external bus master negates BG, after which BD is negated at the completion of the bus cycle. As long as BG is asserted, BD remains asserted to indicate the bus is owned by the MCF5206E and the MCF5206E continuously drives the address bus, attributes and control signals. In the second situation, the bus is granted to the MCF5206E , but the MCF5206E does not have an internal bus request pending and the bus lock bit in the SIMR is cleared. In this case, the MCF5206E takes implicit ownership of the bus. Implicit ownership of the bus occurs when the MCF5206E is granted the bus, but there are no pending bus cycles. The MCF5206E does not drive the bus and does not assert BD if the bus is implicitly owned. If an internal bus request is generated or the bus lock bit in the SIMR is set to 1, the MCF5206E assumes explicit ownership of the bus. If explicit ownership was assumed due to an internal request being generated, the MCF5206E immediately begins an access and simultaneously asserts BD and TS. If explicit ownership was assumed due to the bus lock bit being set to 1, the MCF5206E asserts BD and drives the address, attributes, and control signals. In this case, the MCF5206E is the explicit master of the external bus, but does not begin an access until an internal request is generated. Figure 6-38 illustratesMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E MCF5206E . During C4 and C5, the MCF5206E is implicit owner because an internal access is not pending and the bus lock bit in the SIMR is cleared. During C5, the bus lock bit is set to 1, causing the MCF5206E to take explicit ownership of the bus during C6 by asserting BD. During C7, the external arbiter removes the bus grant from the MCF5206E by negating BG. Because the bus lock bit is set to 1, the MCF5206E does not relinquish the bus (the MCF5206E continues to assert BD) NOTE The MCF5206E can start a transfer during the CLK cycle after BG is asserted. The external arbiter should not assert BG to the MCF5206E until the previous external master has stopped driving the bus. BG cannot be asserted while another external master transfer is still in progress or damage to the part could occur.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-63MCF5206E , one of two situations can occur. In the first case, the bus lock bit in the SIMR is cleared and the MCF5206E has explicit ownership of the bus. When the external bus master negates BG, the MCF5206E completes the current transfer, then negates BD and three-states the address, data, TS, R/W, and SIZ signals after completing the current bus cycle. In the second case, the bus lock bit in the SIMR is set to 1 and the MCF5206E has explicit ownership of the bus. In this case, when the external bus master negates BG, the MCF5206E continues to assert BD and continues to drive address, attributes, and control signals. The MCF5206E retains mastership of the bus until the bus lock bit in the SIMR is cleared. By asserting the bus lock bit, you can select the MCF5206E to be the highest priority master, even when mastership of the bus is controlled by an external arbiter. In this fashion, the MCF5206E can be guaranteed mastership of the bus when executing time-critical, bus-intensive operations. Figure 6-39 illustrates bus arbitration using the bus lock bit to control the arbitration.MCF5206E MCF5206E requests the external bus due to a pending internal transfer. On Clock C3, the external master relinquishes control of the bus and the external arbiter grants the bus to the MCF5206E by asserting bus grant (BG). At this point the bus lock bit is set to 1, and there is an internal access pending so the MCF5206E asserts bus driven (BD) during Clock C4, and begins the access. Thus, the MCF5206E becomes the explicitMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E by negating bus grant (BG). Because the MCF5206E is the current bus master and the bus lock bit in the SIMR is set to 1, it continues to assert BD even after the current transfer has completed. The MCF5206E negates the bus lock bit in the SIMR during C8. Because bus grant (BG) is negated, the MCF5206E negates bus driven (BD) during C9 and three-states the external bus, thereby passing ownership of the external bus to an external master. BR can be used by the external arbiter as an indication that the MCF5206E needs the bus. However, there is no guarantee that when the bus is granted to the MCF5206E , a bus cycle is performed. At best, BR must be used as a status output that indicates when the MCF5206E needs the bus, but not as an indication that the MCF5206E is in a certain bus arbitration state. Figure 6-40, a high level bus arbitration state diagram for the MCF5206E bus arbitration protocol, can be used by external arbiters to predict how the MCF5206E operates as a function of external signals. Table 6-11 lists conditions that cause a change to and from the various states. Table 6-12 describes the MCF5206E bus ownership, bus driving, and assertion of bus driven (BD) for each state of the bus arbitration state machine.MCF5206E Bus Arbitration Protocol State DiagramMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-65MCF5206E Three-Wire Bus Arbitration Protocol Transition ConditionsMCF5206E Three-Wire Arbitration Protocol State DiagramMCF5206E can be in any one of four arbitration states during bus operation: reset, external master own, implicit ownership, and explicit ownership. The reset state is entered whenever RSTI or software watchdog reset is asserted in any bus arbitration state. When RSTI and the software watchdog reset are negated, the MCF5206E proceeds to the implicit ownership state or external master ownership state, depending on bus grant (BG). The external master ownership state denotes the MCF5206E does not have ownership (bus grant (BG) negated) of the bus and the MCF5206E does not drive the bus. TheMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E can assert memory control signals (i.e., CS[7:0], WE[3:0], RAS[1:0] or CAS[3:0]) TA and BR during this state. The implicit ownership state indicates that the MCF5206E owns the bus because bus grant (BG) is asserted to it. The MCF5206E , however, is not ready to begin a bus cycle and the bus lock bit in the SIMR is cleared, and it keeps the bus three-stated until an internal bus request occurs or the bus lock bit in the SIMR is set to 1. The MCF5206E explicitly owns the bus when the bus is granted to it (bus grant (BG) asserted) and at least one bus cycle has initiated or the bus lock bit in the SIMR is set to 1. The MCF5206E asserts BD in this state to indicate the MCF5206E has explicit ownership of the bus. Until bus grant (BG) is negated, the MCF5206E regains explicit ownership of the bus whether or not active bus cycles are being executed. Once bus grant (BG) is negated and the bus lock bit in the SIMR is cleared, the MCF5206E relinquishes the bus at the end of the current bus cycle. When the MCF5206E is ready to relinquish the bus, it negates BD and three-states the bus signals. The bus arbitration state diagram for the MCF5206E three-wire bus arbitration protocol can be used to approximate the high level behavior of the MCF5206E . It is assumed that all TS signals in a system are tied together and each bus master's BD and BR signals are connected individually to the external bus arbiter. The external bus arbiter must be careful to make sure any external bus master has relinquished the bus or will relinquish the bus after the next rising edge of CLK before asserting bus grant (BG) to the MCF5206E . The MCF5206E does not monitor external bus master operation regarding .com bus arbitration. NOTE The MCF5206E can start a transfer on the rising edge of CLK the cycle after BG is asserted. The external arbiter should not assert BG to the MCF5206E until the previous external master has stopped driving the bus. BG cannot be asserted while another external master transfer is still in progress or damage to the part could occur.MCF5206E can monitor bus transfers by other bus masters and can assert chip selects, DRAM control, and transfer termination signals during these transfers. Assertion of chip selects and DRAM control signals can occur when the bus is granted to another bus master and TS is asserted by the external master as an input to the MCF5206E . NOTE External masters that are using internal MCF5206E chip selects, DRAM, and default memory control signals must initiate aligned transfers only.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-67MCF5206E registers the value of A[27:0], R/W, and SIZ[1:0] on the rising edge of CLK in which TS is asserted. NOTE If the pins A[27:24]/CS[7:4]/WE[0:3] are not assigned to output address signals, a value of $0 is assigned internally to A[27:24]. Also, TT[1:0] and ATM are not examined during external master transfers. The mask bits SC, SD, UC, UD and C/I in the Chip Select Mask Registers (CSMR) and in the DRAM Controller Mask Registers (DCMR) are not used during external master transfers.MCF5206E TS pin should not be asserted when bus driven (BD) is negated. This subsection concentrates on external master accesses to default memory. For more information on external master accesses to chip select and DRAM memory spaces, refer to Section 8 Chip Select and Section 10 DRAM Controller. During external master transfers, the.com MCF5206E examines the address, direction, and size of the transfer, and on the next rising edge of CLK, begins assertion of the proper sequence of memory control signals. If the transfer is decoded to be a chip select address and the chip select is enabled for the direction of the transfer (read- and/or write enabled), the appropriate chip selects and write enable signals are asserted. If the chip select is enabled for external master automatic acknowledge, TA is driven and asserted at the appropriate time. The MCF5206E does not drive addresses during external bus master accesses that are decoded as chip select or default memory transfers. The external master must provide the correct address to the external memory at the appropriate time. If the transfer is decoded to be a DRAM address and the DRAM bank is enabled for the direction of the transfer (read- and/or write enabled), the appropriate DRAM control address and the transferacknowledge (TA) signals are asserted. If the address of the transfer is neither a chipselect or a DRAM address, the SIM reads the DMCR. If the external master automatic acknowledge (EMAA) bit in the DMCR is set, the MCF5206E drives TA and asserts transfer acknowledge after the number of clocks programmed in the wait state bits (WS) in the DMCR. For more information about programming the Default Memory Control Register, refer to the SIM section. Table 6-13 lists the signals and conditions under which the MCF5206E drives these signals during external master accesses.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E : if EMAA in CSCR is set to 1 MCF5206E : if DCAR in DCCR is RAS[1:0], CAS[3:0], DRAMW MCF5206E set to 1 External Master MCF5206E : if EMAA in DMCR is set to 1MCF5206E TerminationMCF5206E -generated termination is the same as a ColdFire core initiated transfer with one additional CLK cycle between the assertion of TS by the external master and the starting of the internal waitstate counter by the MCF5206E . During this CLK cycle, the MCF5206E decodes the external master address to determine the appropriate memory control and termination signals that must be asserted. For more information on chip select transfers and DRAM transfers, refer to Section 8 Chip Selects and Section 10 DRAM Controller. Figure 6-41 is a flow chart for external master read transfers using MCF5206E -generated automatic acknowledge to access 8-, 16-, or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for theMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-69MCF5206E MCF5206E -Generated Transfer Acknowledge FlowchartMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E during external master read transfers.MCF5206E Transfer Acknowledge .com Timing (No Wait States) Clock 1 (C1) The read cycle starts in C1. During C1, the external master drives valid values on the address bus (A[27:0]) and transfer control signals. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to indicate the transfer size. The external master asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) At the start of C2, the MCF5206E registers the external master address bus, read/write and size signals. During C2, the MCF5206E decodes the registered address and read/ write signals and if the external master automatic acknowledge (EMAA) bit in the Default Memory Control Register (DMCR) is set to 1, the MCF5206E selects the indicated number of wait states for loading into the internal wait state counter. During C2, the external master negates TS and samples the level of TA. The selected device(s) decodes the address and drives the appropriate data onto the data bus. Clock 3 (C3) At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set to 1 and the number of wait states is zero, the MCF5206E drives TA signal to the assertedMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-71MCF5206E negates TA and drives TA to a high-impedence state after the next rising edge of CLK.MCF5206E TerminationMCF5206E -generated termination is the same as a ColdFire core-initiated transfer with one additional CLK cycle between the assertion of TS by the external master and the start of the internal wait state counter by the MCF5206E . During this CLK cycle, the MCF5206E decodes the external master address to determine the appropriate memory control and termination signals that must be asserted. For more information on chip select transfers, refer to the Chip Selects section. For more information on DRAM transfers, refer to the DRAM Controller section. Figure 6-43 is a flow chart for external master write transfers using MCF5206E -generated automatic acknowledge to access 8-, 16-, or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the .com transfer, and the specific number of cycles needed for each transfer.MCF5206E SYSTEMMCF5206E -Generated Transfer Acknowledge FlowchartMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E during external master write transfers.MCF5206E Transfer.com Acknowledge Timing (No Wait States) Clock 1 (C1) The write cycle starts in C1. During C1, the external master drives valid values on the address bus (A[27:0]) and transfer control signals. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to indicate the transfer size. The external master asserts transfer start (TS) to indicate the beginning of a bus cycle. Clock 2 (C2) At the start of C2, the MCF5206E registers and decodes the external master address bus, read/write and size signals. If the external master automatic acknowledge (EMAA) bit in the Default Memory Control Register (DMCR) is set to 1, the MCF5206E selects the indicated number of wait states for loading into the internal wait state counter. During C2, the external master negates TS, places the data on the data bus (D[31:0]), and samples the level of TA. The selected device(s) decode the address and latch the data when it is ready. Clock 3 (C3) At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set to 1 and the number of wait states is zero, the MCF5206E asserts TA . During C3, the external master samples the level of TA. If TA is asserted, the external master terminatesMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-73MCF5206E negates TA and drives TA to a high impedence state after the next rising edge of CLK.MCF5206E -Generated Transfer TerminationMCF5206E -generated termination is similar to a ColdFire core initiated bursting transfer with the exception that one additional CLK cycle is inserted between the assertion of TS by the external master and the starting of the internal wait state counter by the MCF5206E . If the transfer is to default memory, the external master must increment the address to the appropriate value after each assertion of transfer acknowledge. For more information on chip select transfers, refer to Section 8 Chip Selects. For more information on DRAM transfers, refer to Section 10 DRAM Controller. NOTEMCF5206E generated automatic acknowledge to access 8-, 16-, or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the transfer, and the specific number of cycles needed for each transfer. A bursting read transfer can be from two to sixteen transfers long. The flowchart in Figure 6-45 is for a bursting transfer four transfers long.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E MCF5206E -Generated Transfer-Acknowledge FlowchartMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-75MCF5206E during external master bursting read transfers.MCF5206E Transfer-Acknowledge Timing (No Wait States) Clock 1 (C1) The read cycle starts in C1. During C1, the external master places valid values on the address bus (A[27:0]) and transfer control signals. The read/write (R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate a longword transfer. The external master asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) At the start of C2, the MCF5206E registers the external master address bus, read/write and size signals. During C2, the MCF5206E decodes the registered address and read/ write signals and if the external master automatic acknowledge (EMAA) bit in the Default Memory Control Register (DMCR) is set to 1, the MCF5206E selects the indicated number of wait states for loading into the internal wait state counter. During C2, the external master negates TS and samples the level of TA. The selected device(s) decodes the address and drives the appropriate data onto the data bus.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives TA signal to the asserted state. During C3, the external master samples the level of TA. If TA is asserted, the external master latches the first byte of data from D[31:24]. If TA is negated, the external master continues to insert wait states instead of terminating the transfer. The external master must continue to sample TA on successive rising edges of CLK until it is asserted. Clock 4 (C4) During C4, the external master increments the address by one to access the second byte of data in the longword transfer. The external master also samples the level of TA. If TA is asserted, the external master latches the second byte of data from D[31:24]. If TA is negated, the external master continues to insert wait states instead of terminating the transfer. The external master must continue to sample TA on successive rising edges of CLK until it is asserted. The selected slave decodes the address and outputs the next byte of data on D[31:24]. The MCF5206E continues to assert TA. Clock 5 (C5) This clock is identical to C4 except the external master increments the address to point to .com the third byte of data, and the selected slave decodes the address and outputs the third byte of data of the longword transfer. Clock 6 (C6) This clock is identical to C4 except the external master increments the address to point to the fourth byte of data, and the selected slave decodes the address and outputs the fourth byte of data of the longword transfer. Clock 7 (C7) During C7, the selected slave device drives the data bus to a high impedence state. The MCF5206E drives TA to the inactive state and then drives TA to a high-impedence state after the next rising edge of CLK.MCF5206E -Generated Transfer TerminationMCF5206E -generated termination is similar to a ColdFire core initiated bursting write transfer except that one additional CLK cycle is inserted between the assertion of TS by the external master and the start of the internal wait state counter by the MCF5206E . If the transfer is to default memory, the external master must increment the address to the appropriate value after each assertionMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-77MCF5206E generated automatic acknowledge to access 8-, 16- or 32-bit ports. Bus operations are similar for each case and vary only with the size indicated, the portion of the data bus used for the transfer and the specific number of cycles needed for each transfer. A bursting write transfer can be from two to sixteen transfers long. The flowchart shown in Figure 647 is for a bursting write transfer of four transfers long.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E MCF5206E -Generated Transfer-Acknowledge FlowchartMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-79MCF5206E during external master bursting write transfers.MCF5206E Transfer Acknowledge Timing (No Wait States) Clock 1 (C1) The write cycle starts in C1. During C1, the external master places valid values on the address bus (A[27:0]) and transfer control signals. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate a longword transfer. The external master asserts TS to indicate the beginning of a bus cycle. Clock 2 (C2) At the start of C2, the MCF5206E registers and decodes the external master address bus, read/write and size signals. If the external master automatic acknowledge (EMAA) bit in the Default Memory Control Register (DMCR) is set to 1, the MCF5206E selects the indicated number of wait states for loading into the internal wait state counter. During C2, the external master negates TS, drives the appropriate data onto the data bus, and samples the level of TA. The selected device(s) decodes the address and if ready, latches the appropriate data from the data bus.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E asserts TA. During C3, the external master samples the level of TA. If TA is asserted, the transfer of the first word is complete. If TA is negated, the external master continues to insert wait states instead of terminating the transfer. The external master must continue to sample TA on successive rising edges of CLK until it is asserted. Clock 4 (C4) During C4, the external master increments the address by two to point to the second word of data in the longword transfer and outputs the second word of data onto the data bus. The external master also samples the level of TA. If TA is asserted, the transfer of the second word of the longword transfer is complete. If TA is negated, the external master continues to insert wait states instead of terminating the transfer. The external master must continue to sample TA on successive rising edges of CLK until it is asserted. The selected slave decodes the address and latches the next word of data on D[31:16]. The MCF5206E continues to assert TA. Clock 5 (C5) During C5, the external master drives the data bus to a high impedence state. The MCF5206E drives TA to the inactive .com TA in a high-impedence state after state and places the next rising edge of CLK.MCF5206E supports three types of reset, two of which are external hardware resets (master reset and normal reset) and one internal reset--Software Watchdog reset. Master reset resets the entire MCF5206E including the DRAM controller. Normal reset resets all of the MCF5206E with the exception of the DRAM controller. Normal reset allows DRAM refresh cycles to continue at the programmed rate and with the programmed waveform timing while the remainder of the system is being reset, maintaining the data stored in DRAM. The Software Watchdog resets act as internally generated normal resets. NOTE Master reset must be asserted for all power-on resets. Failure to assert master reset during power-on sequences results in unpredictable DRAM controller behavior.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-81MCF5206E caused by the random manner in which internal flip-flops power up. RSTI and HIZ are internally synchronized on consecutive rising and falling clocks before being used and must meet the specified setup and hold times to the falling edge of he clock only if recognition by a specific CLK falling edge is required.MCF5206E asserts the reset out pin (RSTO). RSTO is asserted as long as RSTI is asserted and remains asserted for 32 CLK cycles after RSTI is negated. For proper master reset operation, RSTI and HIZ must be asserted and negated simultaneously. During the master reset period, all signals that can be are driven to a high-impedence state and all those that cannot be driven to a high-impedence state are driven to their negated states. Once RSTI negates, all bus signals continue to remain in a highimpedance state until the MCF5206E is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing. A master reset causes any bus cycle (including DRAM refresh cycles) to terminate. In addition, master reset initializes registers appropriately for a reset exception. During a master reset, the hard reset bit (HRST) bit in the Reset Status Register (RSR) is set and the software reset bit (SRST) in the Reset Status Register (RSR) is cleared to indicate that an external hardware reset caused the previous reset.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E asserts the reset out pin (RSTO). RSTO is asserted as long as RSTI is asserted and remains asserted for 32 CLK cycles after RSTI is negated. For proper normal reset operation, HIZ must be negated as long as RSTI is asserted. During the normal reset period, all signals that can be are driven to a high-impedence state and all those that cannot are driven to their negated states. Once RSTI negates, allMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-83MCF5206E is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing. A normal reset causes all bus activity except DRAM refresh cycles to terminate. During a normal reset, DRAM refresh cycles continues to occur at the programmed rate and with the programmed waveform timing. In addition, normal reset initializes registers appropriately for a reset exception. During an external normal reset, the hard reset (HRST) bit in the Reset Status Register (RSR) is set and the software reset (SRST) bit in the Reset Status Register (RSR) is cleared to indicate an external hardware reset caused the previous reset. The levels of the IPLx pins select the port size and acknowledge features of the global chip select after an external normal reset occurs. The IPLx signals are synchronized and are registered on the last falling edge of CLK where RSTI is asserted.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E . RSTO is asserted for at least 31 CLK cycles after the internal software watchdog timer reset negated. During the software watchdog timer reset period, all signals that can be are driven to a high-impedence state and all those that cannot are driven to their negated states. Once RSTO negates, all bus signals continue to remain in a high-impedance state until the MCF5206E is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing. A software watchdog timer reset causes all bus activity except DRAM refresh cycles to terminate. During a software watchdog timer reset, DRAM refresh cycles continue to occur at the programmed rate and with the programmed waveform timing. In addition, software watchdog timer reset initializes registers appropriately for a reset exception. During a software watchdog timer reset, the hard reset (HRST) bit in the Reset Status Register (RSR) is cleared and the software reset (SRST) bit in the Reset Status Register (RSR) is set to 1 to indicate that a software watchdog timeout caused the previous reset. NOTE The levels of the IPLx pins are not sampled during a software watchdog reset. If the port size and acknowledge features of the global chip select are different from the values programmed in the Chip Select Control Register 0 (CSCR0) at the time of the software watchdog reset, you must assert RSTI during software watchdog reset to cause the IPLx/IRQx pins to be resampled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 6-85MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E on-chip peripherals do not support the single-address transfer mode. DMA requests may be internally generated by the processor writing to the start bit or externally generated by a device. The amount of bus bandwidth allocated for the DMA can be programmed by the processor for each channel. The DMA channels support two transfer modes: continuous mode and cycle steal mode.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-15MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 7-17MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E . The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire(R) core processor and the internal peripherals or external devices.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E interrupt sources, including: * External Interrupts (IPL/IRQ) * Software watchdog timer * Timer modules * MBUS (I2C) module * UART modules * DMA modulesMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-3MCF5206E acknowledges the interrupt (by generating an interrupt acknowledge cycle) to guarantee that the interrupt is recognized. If the external interrupt inputs are programmed to be interrupt priority levels, the interrupt request must maintain the interrupt request level or a higher priority level request until the MCF5206E acknowledges the interrupt to guarantee that the interrupt is recognized. When the external interrupts are programmed to be individual IRQ interrupts in the Pin Assignment Register (PAR), the interrupt level bits in the appropriate ICRs of the external interrupts are not user-programmable and are always set to 1, 4, and 7. The value of the interrupt level bits in the ICRs for the external interrupts cannot be changed, even by a write to the register. If the external interrupts are programmed to be encoded interrupt priority levels, the interrupt level is that indicated as shown in Table 8-1.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E and the bus is released when bus grant (BG) is negated and the current bus cycle is completed. 1 = Once bus grant (BG) is asserted, the bus driven (BD) signal is asserted and can not be cleared until the BL bit is cleared. 8.3.2.3 INTERRUPT CONTROL REGISTER (ICR). The ICR contains the interrupt levels and priorities assigned to each interrupt input. There is one ICR for each interrupt input. Table 8-3 indicates the interrupt control register assigned to each interrupt input, the interrupt control register reset value, and the value of the interrupt level assigned. Each interrupt input must have a unique interrupt level and interrupt priority combination. NOTE The interrupt control registers do not have valid interrupt level/ interrupt priority combinations out of reset. You must program all interrupt control registers before programming the interrupt mask register (IMR). If you program the external interrupt inputs to be individual interrupts at level 1, 4 and 7, then ICR2, ICR3, ICR5 and ICR6 are not used.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-15MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E as follows: 0 = Set IRQ7/IPL2, IRQ4/IPL1 and IRQ1/IPL0 to be used as individual interrupt inputs at level 7, 4 and 1, respectively. 1 = Set IRQ7/IPL2, IRQ4/IPL1 and IRQ1/IPL0 to be used as encoded interrupt priority level inputs PAR5 - Pin Assignment Bit 5 This bit lets you select the signals output on the pins PP[7:4]/PST[3:0] as follows: 0 = Output general purpose I/O .com on PP[7:4]/PST[3:0] pins signals PP7 - PP4 1 = Output background debug mode signals PST3 - PST0 on PP[7:4]/PST[3:0] pins PAR4 - Pin Assignment Bit 4 This bit lets you select the signals output on the pins PP[3:0]/DDATA[3:0] as follows: 0 = Output Parallel Port output signals PP3 - PP0 on PP[3:0]/DDATA[3:0] pins 1 = Output background debug mode signals DDATA3 - DDATA0 on PP[3:0]/ DDATA[3:0] pins PAR3 - PAR0 - Pin Assignment Bits 3 - 0 These bits let you select the signal output on the pins CS[7:4]/A[27:24]/WE[3:0]. You can select the signals as shown in Table 8-8. Table 8-8. PAR3 - PAR0 Pin AssignmentMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-17MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E to behave similarly to the MCF5206, however DMA transfers are not now .com allowed, since the DMA channels cannot arbitrate for the bus. This functionality has been provided primarily for customers upgrading older MCF5206 designs where the DMA would not be used. NOARB - Arbiter operation disable. 0 = Arbitration enabled 1 = Arbitration disabled (MCF5206 mode) The ARBCTRL bit determines the highest priority on the internal master bus. These options are shown in table 8-9: Table 8-9. Arbitration Control Encodings (ARBCTRL)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 8-19MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E outputs the address and increments the lower bits during burst transfers, allowing the address bus to be directlyMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-3MCF5206E does not output the address during external master initiated transfers to chip select memory.MCF5206E correctly transfers valid data to 8, 16-, and 32-bit ports. Figure 9-1 illustrates the connection of the data bus to 8-, 16-, and 32-bit ports.MCF5206E Interface to Various Port Sizes 9.2.1.5 TRANSFER ACKNOWLEDGE (TA). Transfer acknowledge is a bidirectional signal that indicates the current data transfer has been successfully completed. You can program TA to be output after a programmed number of wait states during external master-initiated transfers that hit in chip select or default memory address space. TA is an input during ColdFire core-initiated transfers that hit in chip select or default memory address space.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E compares the address for the current bus transfer with the address and mask bits in the Chip Select Address Registers (CSARs), DRAM Controller Address Registers (DCARs), the Chip Select Mask Registers (CSMRs), and DRAM Controller Mask Register (DCMRs),MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-5MCF5206E compares the address and mask in chip select 0 - 7 (chip select 0 is compared first), then the address and mask in DRAM 0 - 1. If the address does not match in either or these, the MCF5206E uses the control bits in the Default Memory Control Register (DMCR) to control the bus transfer. If the Default Memory Control Register (DMCR) .com control bits are used, no chip select or DRAM control signals are asserted during the transfer. 9.3.1.2 ACCESS PERMISSIONS. Chip select accesses can be restricted based on transfer direction and attributes. Each chip select can be enabled for read and/or write transfers using the WR and RD bits in the CSCRs. Each chip select can have supervisor data, supervisor code, user data, user code, and only chip select 1 can have CPU space (including interrupt acknowledge) transfers masked from their address space using the SD, SC, UD, UC, and C/I bits in the CSMRs. The transfer address must match, the transfer direction must be enabled, and transfer attributes must be unmasked for a chip select to assert. 9.3.1.3 CONTROL FEATURES. The chip select control registers and the default memory control register are used to program timing and assertion features of the chip selects. The chip select control register provides the following programmable control features: * Port size (8-, 16- or 32-bit) * Number of internal wait states (0 - 15) * Enable assertion of internal transfer acknowledge * Enable assertion of transfer acknowledge for external master transfers * Enable burst transfersMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E initiated transfers for each chip select and default memory individually. Transfer acknowledge (TA) can synchronously terminate a transfer. If the MCF5206E initiates a bus transfer and internal termination is enabled (but TA is asserted before the specified number of wait states have been inserted), the transfer terminates on the CLK cycle where TA is asserted. NOTE If an external master .com transfer and internal initiates a bus termination is enabled, TA should not be driven by an external device. The MCF5206E drives TA throughout the external master access. Asynchronous transfer acknowledge (ATA) can asynchronously terminate a chip select or default memory transfer. If the MCF5206E initiates a bus transfer and internal termination is enabled but ATA is asserted before the specified number of wait states have been inserted, the transfer terminates on the CLK cycle where the internal asynchronous transfer acknowledge is asserted. If an external master initiates a bus transfer and internal termination is enabled, ATA can be driven by an external device to terminate the transfer before the specified number of wait states has been inserted. In this case, the transfer terminates when the internal asynchronous transfer acknowledge is asserted. 9.3.1.3.3 Bursting Control. The general-purpose chip selects support burst and nonbursting peripherals and memory. If an external chip select device cannot be accessed using burst transfers, you can program the burst-enable bit in the appropriate chip select Control Register (CSCR) or in the Default Memory Control Register (DMCR) to a 0. If the burst-enable bit is set to 1, burst transfers are generated anytime the requested operand size is greater than the programmed chip select or default memory port size. If the burst enable bit is set to 0, nonburst transfers are always generated for the particular chip select or default memory access. Figure 9-5, Figure 9-6, and Figure 9-7 illustrate burst transfers with various settings of address setup, address hold, and 0 wait states.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-7MCF5206E uses the address bus (A[27:0]) to specify the location for a data transfer and the data bus (D[31:0]) to transfer the data. Chip selects are asserted during bus transfers where the address, transfer direction and type are not masked for the particular chip select. Write enables are asserted on write transfers and indicate the valid byte lanes for the transfer. Write enables are always asserted on the CLK cycle after the chip select is asserted. Chip select and write enables can be asserted during burst and burst inhibited transfers. The assertion and negation timing of the chip selects are controlled by the address setup, read address hold, and write address hold bits in the chip select control registers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven low to identify the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven low to indicate a longword transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle and asserts the appropriate chip select (CS) for the address being accessed. Clock 2 (C2)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-9MCF5206E negates transfer start (TS), drives access type and mode (ATM) high to identify the transfer as supervisor and drives data onto D[31:0]. If the selected device(s) is ready to latch the data, it latches D[31:0] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206E samples the level of TA. If TA is asserted, the transfer of the longword is complete, and the MCF5206E negates CS and WE[3:0] after the next rising edge of CLK. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. 9.3.3.2 NONBURST TRANSFER WITH ADDRESS SETUP. Figure 9-3 illustrates a word user data write transfer to a 16-bit port with address setup enabled..MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven low to identify the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. The chip select (CS) signal is driven high since the appropriate address setup bit in the chip select control register is set to 1.MCF5206E negates transfer start (TS), drives access type and mode (ATM) low to identify the transfer as user and drives data onto D[31:16] and asserts the appropriate chip select (CS) signal. At the end of C2, the MCF5206E samples the level of TA. If TA was asserted the transfer of the word would be complete. Since TA is negated, the MCF5206E continues to output the data and inserts a wait state instead of terminating the transfer. Clock 3 (C3) The MCF5206E asserts the write enable (WE[1:0]) signals. If the selected device(s) is .com ready to latch the data, it latches D[31:0] and asserts the transfer acknowledge (TA). At the end of C3, the MCF5206E samples the level of TA . If TA is asserted, the transfer of the word is complete, and the MCF5206E negates CS and WE[1:0] after the rising edge of CLK. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is be terminated with an internal bus error. NOTE When address setup is enabled (ASET=1), write enables (WE[3:0]) do not assert on zero wait state write transfers. 9.3.3.3 NONBURST TRANSFER WITH ADDRESS SETUP AND HOLD. Figure 9-4 illustrates a supervisor data byte write transfer to an 8-bit port with address setup and write address hold enabled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-11MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven low to identify the transfer as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. The chip select (CS) signal is driven high since the appropriate address setup bit in the chip select control register is set to 1. Clock 2 (C2)MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates transfer start (TS), drives access type and mode (ATM) high to identify if the transfer as supervisor, drives data onto D[31:16] and asserts the appropriate chip select (CS). At the end of C2, the MCF5206E samples the level of TA. If TA was asserted the transfer of the word would be complete. Since TA is negated, the MCF5206E continues to output the data and inserts a wait state instead of terminating the transfer. Clock 3 (C3) The MCF5206E asserts the write enable (WE[1:0]) signals. If the selected device(s) is ready to latch the data, it latches D[31:0] and asserts the transfer acknowledge (TA). At the end of C3, the MCF5206E samples the level of TA. If TA is asserted, the transfer of the word is complete. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. Clock 4 (C4) The MCF5206E negates the chip select (CS) and write enable (WE[1:0]) signals and continues to drive the address, data and attribute signals until after the next rising edge of CLK.MCF5206E performs word, longword and line transfers in burst mode. When burst mode is selected, the size of the transfer (indicated by SIZ[1:0]) reflects the size of the operand being read - not the size of the port being accessed (i.e. a line transfer is indicated by SIZ[1:0] = $3 and a longword transfer is indicated by SIZ[1:0] = $0, regardless of the size of the port or the number of transfers required to access the data). The MCF5206E supports burst-inhibited transfers for memory devices that are unable to support bursting. For this type of bus cycle, the burst enable bit in the Chip Select Control Registers (CSCRs) or Default Memory Control Register (DMCR) must be cleared. Figure 9-5 illustrates a supervisor code longword read transfer to a 16-bit port with address setup and address hold disabled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-13MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven high to identify the transfer as code. The read/write (R/W) and write enable (WE[3:0]) signals are driven high for a read cycle, and the size signals (SIZ[1:0]) are driven low to indicate a longword transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle and asserts the appropriate chip select (CS) for the address being accessed. Clock 2 (C2) During C2, the MCF5206E negates transfer start (TS), drives access type and mode (ATM) high to identify the transfer as supervisor. The selected device(s) places the addressed data onto D[31:16] and asserts the transfer acknowledge (TA). At the end ofMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of the first word of the longword is complete. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. Clock 3 (C3) During C3, the MCF5206E increments A[1:0] to indicate the second word in the longword transfer. The selected device(s) places the addressed data onto D[31:16] and asserts the transfer acknowledge (TA). At the end of C3, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of the second word of the longword is complete and the transfer terminates and the chip select (CS) is negated. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. 9.3.3.5 BURST TRANSFER WITH ADDRESS SETUP. Figure 9-6 illustrates a longword user code read from a 16-bit port with address setup enabled and read address hold disabled. .comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-15MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven high to identify the transfer as reading code. The read/write (R/W) and write enable (WE[3:0]) signals are driven high for a read cycle, and the size signals (SIZ[1:0]) are driven low to indicate a longword transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. The chip select (CS) signal is driven high since the appropriate address setup bit in the chip select control register is set to 1.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates transfer start (TS), drives access type and mode (ATM) low to identify if the transfer as user. The appropriate chip select (CS) signal is asserted. The selected device(s) places the addressed data onto D[31:16] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of the first word of the longword is complete and chip select (CS) is negated after the next rising edge of CLK. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. Clock 3 (C3) During C3, the MCF5206E increments A[1:0] to indicate the second word in the longword transfer. The chip select (CS) signal is driven high since the appropriate address setup bit in the chip select control register is set to 1. Clock 4 (C4) The selected device(s) places the addressed data onto D[31:16] and asserts the transfer acknowledge (TA). At the end of C4, the MCF5206E samples the level of TA and if TA is .com asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of the second word of the longword is complete and the transfer terminates and the chip select (CS) is negated. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. NOTE When address setup is enabled (ASET=1), write enables (WE[3:0]) do not assert on zero wait state write transfers. 9.3.3.6 BURST TRANSFER WITH ADDRESS SETUP AND HOLD. Figure 9-7 illustrates a supervisor data word read transfer from an 8-bit port with address setup and read address hold enabled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-17MCF5206E places valid values on the address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the specific access type and access type and mode (ATM) is driven low to identify the transfer as reading data. The read/write (R/W) and write enable (WE[3:0]) signals are driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206E asserts transfer start (TS) to indicate the beginning of a bus cycle. The chip select (CS) signal is driven high since the appropriate address setup bit in the chip select control register is set to 1.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates transfer start (TS), drives access type and mode (ATM) high to identify the transfer as supervisor. The appropriate chip select (CS) signal is asserted. The selected device(s) places the addressed data onto D[31:24] and asserts the transfer acknowledge (TA). At the end of C2, the MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the first byte of the word is complete and chip select (CS) is negated after the next rising edge of CLK. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. Clock 3 (C3) The MCF5206E continues to drive address and bus attributes since the read address hold bit in the appropriate chip select control register is set to 1. Clock 4(C4) During C3, the MCF5206E increments A[0] to indicate the second byte in the word transfer. The chip select (CS) signal is driven high since the appropriate address setup bit in the chip select control register is set to 1.MCF5206E samples the level of TA and if TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the second word of the longword is complete and the transfer terminates and the chip select (CS) is negated. If TA is negated, the MCF5206E continues to sample TA and inserts wait states instead of terminating the transfer. The MCF5206E continues to sample TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted before the programmed bus monitor time is reached, the cycle is terminated with an internal bus error. Clock 6 (C6) The MCF5206E continues to drive address and bus attributes since the read address hold bit in the appropriate chip select control register is set to 1. NOTE When address setup is enabled (ASET=1), write enables (WE[3:0]) do not assert on zero wait state write transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-19MCF5206E can monitor bus transfers by other bus masters and assert chip select and transfer termination signals during these transfers. Assertion of chip select and termination signals occurs when the bus is granted to another bus master and TS is asserted by the external master as an input to the MCF5206E . The MCF5206E registers the value of A[27:0], R/W and SIZ[1:0] on the rising edge of CLK in which TS is asserted. NOTE If the pins A[27:24]/CS[7:4]/WE[0:3] are not assigned to output address signals, a value of $0 is assigned internally to these signals. Also, TT[1:0] and ATM are not examined during external master transfers. The mask bits: SC, SD, UC, UD, and C/I in the Chip Select Mask Registers (CSMR) are not used during external master transfers. The MCF5206E examines the address, direction and size of the transfer and on the next rising edge of CLK, begins assertion of the proper sequence of memory control signals. If the transfer is decoded to be a chip select address and the chip select is enabled for the direction of the transfer (read and/or write enabled), the appropriate chip select and write enables are asserted. If the chip select is enabled for external master automatic acknowledge, TA is driven and asserted at the appropriate time. The MCF5206E does not drive address during external bus master accesses that are decoded as chip select or .com default memory transfers. The external master must provide the correct address to the external memory at the appropriate time. If the address of the transfer is neither a chip select or a DRAM address, the SIM reads the Default Memory Control Register (DMCR). If the external master automatic acknowledge (EMAA) bit in the Default Memory Control Register (DMCR) is set, the MCF5206E drives transfer acknowledge (TA) as an output and asserts transfer acknowledge after the number of clocks programmed in the wait state bits (WS) in the Default Memory Control Register (DMCR). 9.3.4.1 EXTERNAL MASTER NONBURST TRANSFER. The general-purpose chip selects support burst and nonbursting peripherals and memory for external master accesses. If an external chip select device can not be accessed using burst transfers, you can program the burst-enable bit in the appropriate Chip Select Control Register (CSCR) or in the Default Memory Control Register (DMCR) to a 0. If the burst-enable bit is set to 1, and the external master initiates a transfer where the transfer size is greater than the programmed port size, the MCF5206E asserts the chip select control signals for a burst transfer. If the burst enable bit is set to 0, the external master should never initiate a transfer with the size specified as larger than the programmed port size. Figure 9-8 illustrates a longword read transfer initiated by an external master to a 32-bit port.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E registers the external master address, read/write and size signals. Clock 2 (C2) During C2, the external master negates transfer start (TS). The MCF5206E compares the external master address to the internal chip select addresses and enables the appropriate chip select for assertion. Clock 3 (C3) The MCF5206E asserts the appropriate chip select and since the EMAA bit in the appropriate Chip Select Control Register (CSCR) is set to one, asserts transfer acknowledge (TA). The selected device drive data onto D[31:0]. At the end of C3, the external master samples the level of TA. If TA is asserted, the transfer of the longword isMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-21MCF5206E negates CS and TA, completing the external master transfer. After the next rising edge of CLK, the MCF5206E three states TA. The external master can assert TS starting another transfer. 9.3.4.2 EXTERNAL MASTER BURST TRANSFER. The timing of the assertion and negation of the general-purpose chip selects and write enables during external master accesses can be programmed on a chip select basis. The address setup and hold features of the chip selects are not used during nonburst external master accesses. The address setup and hold features can insert CLK cycles where the chip select is negated, during burst cycles. During external master read transfers, the MCF5206E drives the activated chip select signal negated for one CLK cycle for each of the address setup and read address hold bits that are set to 1. During external master write transfers, the MCF5206E drives the activated chip select signal negated for one CLK cycle for each of the address setup and write address hold bits that are set to 1. Figure 9-9 illustrates a bursting longword read transfer from a 16-bit port with no address setup and no address hold.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E registers the external master address, read/write and size signals. Clock 2 (C2) During C2, the external master negates transfer start (TS). The MCF5206E compares the external master address to the internal chip select addresses and enables the appropriate chip select and transfer acknowledge (TA) for assertion. Clock 3 (C3) The MCF5206E asserts the appropriate chip select and since the EMAA bit in the appropriate Chip Select Control Register (CSCR) is set to one and wait states are set to zero, asserts transfer acknowledge (TA). The selected device drives data onto D[31:16]. At the end of C3, the external master samples the level of TA. If TA is asserted, theMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-23MCF5206E continues to assert CS and TA and the selected slave outputs the data indicated by the new address on D[31:16]. At the end of clock 4, the external master samples the level of TA. If TA is asserted, the transfer of the second word of the longword is complete. If TA is negated, the external master continues to sample TA and inserts wait states instead of terminating the transfer. Clock 5 (C5)MCF5206E negates CS and TA, completing the external master transfer. After the next rising edge of CLK, the MCF5206E three states TA. The external master can assert TS starting another transfer. NOTE Write enables (WE[3:0]) do not assert on zero wait state external master write transfers. 9.3.4.3 EXTERNAL MASTER BURST TRANSFER WITH ADDRESS SETUP AND .com HOLD. Figure 9-10 illustrates a longword bursting read transfer from a 16-bit port with either address setup or read address hold enabled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E registers the external master address, read/write and size signals. Clock 2 (C2) During C2, the external master negates transfer start (TS). The MCF5206E compares the external master address to the internal chip select addresses and enables the appropriate chip select and transfer acknowledge (TA) for assertion. Clock 3 (C3) The MCF5206E asserts the appropriate chip select and since the EMAA bit in the appropriate Chip Select Control Register (CSCR) is set to one and wait states are set to zero, asserts transfer acknowledge (TA). The selected device drives data onto D[31:16]. At the end of C3, the external master samples the level of TA. If TA is asserted, theMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-25MCF5206E negates CS and TA. Clock 5 (C5) At the start of clock 5, the MCF5206E asserts CS and TA. The selected slave outputs the data indicated by the address on D[31:16]. At the end of clock 4, the external master samples the level of TA. If TA is asserted, the transfer of the second word of the longword is complete. If TA is negated, the external master continues to sample TA and inserts wait states instead of terminating the transfer. After the next rising edge of CLK, the MCF5206E negates CS and TA, completing the external master transfer. After the next rising edge of CLK, the MCF5206E three states TA. The external master can assert TS starting another transfer. NOTE Write enables (WE[3:0]) do not assert on zero wait state external master write transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-27MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-29MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-31MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-33MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-35MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-37MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-39MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-41MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 9-43MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E provides eight general-purpose input/output signals that can be used on a pin-by-pin basis. This subsection describes the operation and programming model of the parallel port registers and the direction-control and data registers.MCF5206E parallel port module has eight signals that you can select as inputs or outputs on a pin-by-pin basis. These pins are multiplexed with the MCF5206E emulation pins and are programmed to their parallel port function through the Pin Assignment Register (PAR). Refer to the SIM subsection 6.3.2.10 Pin Assignment Register for programming description.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 10-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-3MCF5206E correctly transfers valid data to 8, 16 and 32-bit ports. Figure 11-1 illustrates the connection of the data bus to 8-, 16-, and 32-bit ports.MCF5206E Interface to Various Port SizesMCF5206E supports two types of external hardware reset--Master Reset and Normal Reset. Master Reset resets the entire MCF5206E including all functions of the DRAMC. Normal Reset resets all of the functions of the MCF5206E with the exception of the DRAMC Refresh Controller. During Normal Resets, the Refresh Controller continues to generate refresh cycles at the programmed rate and with the programmed cycle timing.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E registers are reset to the same values during normal resets as during Master Resets. During normal reset, DRAM refreshes occurs at the programmed rate and with the programmed DRAM cycle timing. A normal reset is accomplished by asserting the RSTI signal while negating the HIZ signal. Resets generated by the internal software watchdog timer are normal resets.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-5MCF5206E . The output of A[27:24] are dependent on the setting of PAR3-PAR0 in the Pin Assignment Register (PAR) in the SIM. NOTE The MCF5206E compares the address for the current bus transfer with the address and mask bits in the Chip Select Address Registers (CSARs), DRAM Controller Address Registers (DCARs) and the Chip Select Mask Registers (CSMRs) and DRAM Controller Mask Register (DCMRs),MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E compares the address and mask in chip select 0 - 7 (chip select 0 is compared first), then the address and mask in DRAM 0 - 1. If the address does not match in either or these, the MCF5206E uses the control bits in the Default Memory Control Register (DMCR) to control the bus transfer. If the Default Memory Control Register (DMCR) control bits are used, no chip select or DRAM control signals are asserted during the transfer.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-7MCF5206E provides internal address multiplexing of the row address and column address for DRAM transfers. The internal address multiplexing is used for all ColdFire core initiated DRAM transfers and can selectively be used for external master initiated DRAM transfers. No external logic is required in the system to handle DRAM address multiplexing when the internal multiplexing is used. In addition, the multiplexing scheme allows a single printed circuit board layout to support multiple DRAM memory sizes (allowing for easy memory upgrades). A subset of the address pins should be connected directly to the address inputs of the DRAM to supply the row address and column address. The DRAM port size and bank page size determine which address pins should be connected to the address inputs of the DRAM. In Figure 11-2, the address multiplexing scheme is illustrated for an 8-bit DRAM with 9 address inputs using a 512 byte page size (PS=01 and BPS=00 in the DCCR). In this case, the DRAM address inputs (DA[x]) would be connected to the MCF5206E MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives the internal transfer address IA[27:0] onto the MCF5206E address pins A[27:0] and asserts RAS. This places the internal transfer address bits IA[17:9] into the DRAM as the row address. Then the MCF5206E internally multiplexes and drive the internal transfer address bits IA[8:0] onto the MCF5206E address pins A[17:9] and asserts CAS. This places the internal transfer address bits IA[8:0] into the DRAM as the column address.MCF5206E ADDRESS PINS A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] DRAM ADDRESS INPUTS DA[8] DA[7] DA[6] DA[5] DA[4] DA[3] DA[2] DA[1] DA[0]MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E ADDRESS PIN PS = 8-BIT BPS = 512 BYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] IA[9] COLUMN ADDRESS IA[26] IA[26] IA[24] IA[24] IA[22] IA[22] IA[20] IA[20] IA[18] IA[18] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] MCF5206E ADDRESS PIN PS = 8-BIT BPS = 1 KBYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] COLUMN ADDRESS IA[26] IA[26] IA[24] IA[24] IA[22] IA[22] IA[20] IA[20] IA[9] IA[8] IA[7] IA[6] IA[5] MCF5206E ADDRESS PIN PS = 8-BIT BPS = 2 KBYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] IA[9] COLUMN ADDRESS IA[26] IA[26] IA[24] IA[24] IA[22] IA[22] IA[10] IA[9] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[0] IA[10] IA[9]MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-11MCF5206E ADDRESS PINMCF5206E ADDRESS PIN PS = 16-BIT BPS = 1 KBYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] COLUMN ADDRESS IA[27] IA[25] IA[25] IA[23] IA[23] IA[21] IA[21] IA[19] IA[19] IA[9] IA[8] IA[7] MCF5206E ADDRESS PIN PS = 16-BIT BPS = 2 KBYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] IA[9] COLUMN ADDRESS IA[27] IA[25] IA[25] IA[23] IA[23] IA[21] IA[21] IA[10] IA[9] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[1] IA[10] IA[9]MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E ADDRESS PIN PS = 32-BIT BPS = 512 BYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] IA[9] CAS IA[26] IA[26] IA[24] IA[24] IA[22] IA[22] IA[20] IA[20] IA[18] IA[18] IA[16] IA[16] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] MCF5206E ADDRESS PIN PS = 32-BIT BPS = 1 KBYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] CAS IA[26] IA[26] IA[24] IA[24] IA[22] IA[22] IA[20] IA[20] IA[18] IA[18] IA[9] IA[8] IA[7] MCF5206E ADDRESS PIN PS = 32-BIT BPS = 2 KBYTE ROW ADDRESS IA[27] IA[26] IA[25] IA[24] IA[23] IA[22] IA[21] IA[20] IA[19] IA[18] IA[17] IA[16] IA[15] IA[14] IA[13] IA[12] IA[11] IA[10] IA[9] CAS IA[26] IA[26] IA[24] IA[24] IA[22] IA[22] IA[20] IA[20] IA[10] IA[9] IA[8] IA[7] IA[6] IA[5] IA[4] IA[3] IA[2] IA[10] IA[9]MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-13MCF5206E address pins A[10:19] and A[21] are connected to the DRAM address inputs A[0:10] (see Figure 11-3). For the 1 M x 8 DRAM, the MCF5206E address pins A[10:19] are connected to the DRAM address inputs A[0:9] (see Figure 11-4). Because the address connections for the 1 M x 8 are a subset of those for the 4 M x 8, the address multiplexing scheme allows a system using the MCF5206E to upgrade the memory size without requiring different printed circuit board layouts. The only required change is the number of bits masked in the DCMR. It should be noted that the page size, in this example, is determined by the 1 M x 8 DRAM (9 column address bits gives a page size of 1 KByte), and that even though the 4 M x 8 DRAM could support a 2 KByte page size, the page size must be programmed to 1 KByte to keep the address multiplexing the same.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E A[13] A[12] A[11] A[10] RAS[0] CAS[0] DRAMW D[31:24] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RAS CAS WE D[7:0] 4M x 8 DRAMMCF5206E A[12] A[11] A[10] RAS[0] CAS[0] DRAMW D[31:24] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RAS CAS WE D[7:0] 1M x 8 DRAMMCF5206E supplies a row address on the address bus, drives DRAMW to indicate whether a read or a writeMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-15MCF5206E then drives the column address onto the same address pins and asserts CAS. When the cycle is complete, both RAS and CAS are negated. 11.3.3.1 NONBURST TRANSFER IN NORMAL MODE. A nonburst transfer to DRAM occurs when the operand size is the same or smaller than the DRAM port size (e.g.,longword transfer to a 32-bit port, or byte transfer to a 16-bit port). Nonburst transfers always start with the assertion of TS. The start of a transfer to a DRAM bank can be delayed by the DRAMC until the programmed RAS precharge time is met. A transfer to a different DRAM bank than the previous transfer is never delayed due to RAS precharge because that bank has already been precharged. The timing of nonburst reads and nonburst writes is identical in normal page mode, with the exception of when the DRAM drives data on reads and when the MCF5206E drives data on writes. The fastest possible nonburst transfer in normal mode requires 3 clocks with a 1.5 clock RAS precharge time. You can program the DCTR to generate slower normal mode transfers. Figure 11-5 shows the timing of a back-to-back nonburst byte-read transfer to an 8-bit port in normal mode.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives the row address on the A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $1 indicating a byte transfer, and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on the address bus. Clock H2 The MCF5206E negates TS and drives the column address on the address bus. Clock L2 The MCF5206E asserts CAS[0] to indicate the column address is valid on the address bus. At this point, the DRAM turns on its output drivers and begins driving data on D[31:24].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-17MCF5206E registers the read data driven by the DRAM and negates the internal transfer acknowledge, RAS and CAS[0], ending the first byte-read transfer. This begins the RAS precharge. Once CAS[0] is negated, the DRAM disables its output drivers, and the data bus is three-stated. Clock H6 Clock H6 is the earliest the next transfer initiated by the ColdFire core can start. The second DRAM byte-read transfer starts in H6. During H6, the MCF5206E drives the row address on the A[27:9], drives DRAMW high indicating a DRAM-read transfer, drives SIZ[1:0] to $1 indicating a byte transfer, and asserts TS. Clock L6 The MCF5206E asserts RAS to indicate the row address is valid on the address bus. Clock H7MCF5206E negates TS and drives the column address on the address bus. Clock L7 The MCF5206E asserts CAS[0] to indicate the column address is valid on the address bus. At this point, the DRAM turns on its output drivers and begins driving data on D[31:24]. Clock H8 The internal transfer acknowledge asserts to indicate that the current transfer will be completed and the data on the D[31:24] will be registered on the next rising edge of CLK. Clock H9 The MCF5206E registers the read data driven by the DRAM and negates the internal transfer acknowledge, RAS and CAS[0], ending the first byte-read transfer. This begins the RAS precharge. Once CAS[0] is negated, the DRAM disables its output drivers, and the data bus is three-stated. 11.3.3.2 BURST TRANSFER IN NORMAL MODE. A burst transfer to DRAM is generated when the operand size is larger than the DRAM bank port size (e.g., line transfer to a 32-bit port, longword transfer to an 8-bit port). On all DRAM transfers, theMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E asserts TS only once. The start of the secondary transfers of a burst is delayed by the DRAMC until the programmed RAS precharge time is reached. The timing of burst reads and burst writes is identical in normal page mode, with the exception of when the DRAM drives data on reads and when the MCF5206E drives data on writes. The fastest possible burst transfer in normal mode requires 3 clocks for the first transfer of the burst and 4 clocks for the secondary transfers (including a 1.5 clock RAS precharge time). You can program the DCTR to generate slower normal mode transfers. Figure 11-6 shows the timing of a burst longword write transfer to a 16-bit port in normal mode.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-19MCF5206E drives the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives SIZ[1:0] to $0 indicating a longword transfer, and asserts TS. The address driven on the A[27:9] corresponds to the DRAM row address for the first transfer of the burst. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9].MCF5206E negates TS, drives the column address on A[27:9], and begins driving the data on D[31:16] for the first word write of the longword burst. Clock L2 The MCF5206E asserts CAS[1:0] to indicate the column address is valid on the A[27:9]. Clock H3 The internal transfer acknowledge asserts to indicate the first word transfer of the longword burst will be completed on the next rising edge of CLK. Clock H4 The MCF5206E negates the internal transfer acknowledge, RAS and CAS[1:0], ending the first word write transfer of the longword burst. This begins the RAS precharge. The MCF5206E drives the row address on A[27:9], and begins driving the data on D[31:16] for the second word write of the longword burst. Clock L4/H5 The MCF5206E continues to negate RAS to meet the precharge time. Clock L5MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H6 The MCF5206E drives the column address on A[27:9]. Clock L6 The MCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. Clock H7 The internal transfer acknowledge asserts to indicate the first word transfer of the longword burst will be completed on the next rising edge of CLK. Clock H8 The MCF5206E negates the internal transfer acknowledge, RAS and CAS[1:0], ending the second word write transfer of the longword burst. This begins the RAS precharge. When the burst write is completed, D[31:0] is three-stated.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E loses bus mastership 4. A refresh cycle is pending In each of these cases, the RAS negates and the DRAMC does not allow an access to that bank until the RAS precharge time is met. 11.3.4.1 BURST TRANSFER IN FAST PAGE MODE. A burst transfer to DRAM is generated when the operand size is larger than the DRAM bank port size (e.g., line transfer to a 32-bit port, longword transfer to an 8-bit port). Burst transfers can access from two to 16 segments of data in a single transfer. On all DRAM transfers the MCF5206E asserts TS only once. The internal TA is asserted to indicate the transfer of each segment of data. The start of the secondary transfers of a burst are delayed by the DRAMC until the programmed RAS precharge time is reached. The timing of burst reads and burst writes is identical in fast page mode, with the exception of when the DRAM drives data on reads and when the MCF5206E drives data on writes. The fastest possible burst transfer in normal mode takes 3 clocks for the initial transfer, 2 clocks for secondary transfers with a 0.5 clock CAS precharge time and a 1.5 clock RAS precharge time. You can program the DCTR to generate slower fast page mode transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-21MCF5206E drives the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives SIZ[1:0] to $2 indicating a word transfer, and asserts TS. The address driven on A[27:9] corresponds to the row address for the first byte transfer of the burst. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H2 The MCF5206E negates TS, drives the column address on A[27:9], and begins driving the data on D[31:24]. Clock L2MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates the internal transfer acknowledge, and CAS[0] ending the first byte write transfer of the word burst. At this point, the new page has been opened; therefore, the MCF5206E continues to assert RAS. The negation of CAS[0] begins the CAS precharge. The MCF5206E drives the next column address on A[27:9] and the next data is driven on D[31:24]. Clock L4MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. Clock H5 The internal transfer acknowledge asserts to indicate that the first byte transfer of the word burst will be completed on the next rising edge of CLK. Clock H6 The MCF5206E negates the internal transfer acknowledge and CAS[0] ending the final byte write of the word burst. Because .com page mode, MCF5206E continues the bank is in fast to assert RAS. The negation of CAS[0] begins the CAS precharge. When the burst write is completed, the MCF5206E three-states D[31:0]. 11.3.4.2 PAGE HIT READ TRANSFER IN FAST PAGE MODE. A read transfer to an open page results in a page-hit read. The timing of page-hit reads differs from the timing of page-hit writes (page-hit writes are described in Section 11.3.4.3 Page-Hit Write Transfer in Fast Page Mode). The start of a page-hit read transfer to a DRAM bank in fast page mode can be delayed by the DRAMC until the programmed CAS precharge time is reached. The fastest possible nonburst page-hit read transfer in fast page mode takes 2 clocks with a 0.5 clock CAS precharge time. The fastest possible burst page-hit read transfer in fast page mode takes 2 clocks for the initial transfer, and 2 clocks for all secondary reads with a 0.5 clock CAS precharge time. You can program the DCTR to generate slower fast page mode transfers. Figure 11-8 shows the timing of a nonburst read opening a page and a subsequent pagehit read being generated. The first transfer that opens the page is a longword read transfer from a 32-bit port in fast page mode. The first read transfer is followed by a second pagehit longword read transfer. The timing of a page-hit read transfer is the same regardless of whether the page was opened by a burst read, burst write, nonburst read, or nonburst write transfer.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-23MCF5206E drives the row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $0 indicating a longword transfer, and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H2 The MCF5206E negates TS, and drives the column address on A[27:9].MCF5206E asserts CAS[3:0] to indicate the column address is valid on A[27:9]. At this point the DRAM turns on its output drivers and drives data on D[31:0].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E negates the internal transfer acknowledge and CAS[3:0], ending the longword read transfer. At this point the new page has been opened; therefore, the MCF5206E continues to assert RAS. Once CAS[3:0] are negated the DRAM three-states D[31:0]. The negation of CAS[3:0] begins the CAS precharge. Clock H6MCF5206E drives the column address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $0 indicating a longword transfer, and asserts TS. Clock L6 The MCF5206E asserts CAS[3:0] to indicate the column address is valid on A[27:9]. At this point, the DRAM drives data on D[31:0]. Clock H7MCF5206E negates the internal transfer acknowledge and CAS[3:0], ending the page-hit longword read transfer. Since the DRAM bank is in Fast Page Mode, the MCF5206E continues to assert RAS. Once CAS[3:0] are negated the DRAM three-states D[31:0]. The negation of CAS[3:0] begins the CAS precharge. 11.3.4.3 PAGE-HIT WRITE TRANSFER IN FAST PAGE MODE. A write transfer to an open page results in a page-hit write. The timing of page-hit write transfers differs from the timing of page-hit read transfers. On a page-hit write transfer, CAS is asserted one cycle later than in a page-hit read transfer. This difference is due to the write data not being driven until the cycle after TS is asserted while data must be set up prior to CAS assertion. The start of a page-hit write transfer to a DRAM bank in fast page mode can be delayed by the DRAMC until the programmed CAS precharge time is reached. The fastest possible nonburst page-hit write transfer in fast page mode requires 3 clocks. The fastest possible burst page-hit write transfer in fast page mode requires 3 clocks for the initial transfer and 2 clocks for all secondary writes. You can program the DCTR to generate slower fast page mode transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-25MCF5206E drives the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives SIZ[1:0] to $2 indicating a word transfer, and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H2 The MCF5206E negates TS, drives the column address on A[27:9], and begins driving the data on D[31:16].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. Clock H3 The internal transfer acknowledge asserts to indicate that the word write transfer will be completed on the next rising edge of CLK. Clock H4 The MCF5206E negates the internal transfer acknowledge and CAS[1:0], ending the first word write transfer. At this point, the new page has been opened; therefore, the MCF5206E continues to assert RAS. The negation of CAS[1:0] begins the CAS precharge. When the write is completed, the MCF5206E three-states D[31:0]. Clock H6 Clock H6 is the earliest the next transfer initiated by the ColdFire core can start. In this case, a page-hit word write transfer is shown. The word write transfer starts in H6. During H6, the MCF5206E drives the column address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives SIZ[1:0] to $2 indicating a word transfer, and asserts TS. Clock H7 The MCF5206E negates TS, drives the column address on A[27:9], and begins driving the .com data on D[31:16]. Clock L7 The MCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. Clock H8 The internal transfer acknowledge asserts to indicate that the word write transfer will be completed on the next rising edge of CLK. Clock H9 The MCF5206E negates the internal transfer acknowledge and CAS[1:0], ending the second word write transfer. Because the DRAM bank is in fast page mode, the MCF5206E continues to assert RAS. The negation of CAS[1:0] begins the CAS precharge. When the write is completed, the MCF5206E three-states D[31:0]. 11.3.4.4 PAGE MISS TRANSFER IN FAST PAGE MODE. There is a potential performance penalty when using fast page mode. If a DRAM transfer misses the open page, the start of the transfer will be delayed while RAS precharges. Therefore, fast page mode can increase performance when many successive transfers hitMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-27MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives the row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $1 indicating a byte transfer, and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H2 The MCF5206E negates TS, and drives the column address on A[27:9].MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives data on D[31:24]. Clock H3 The internal transfer acknowledge asserts to indicate that the byte read transfer will be completed and data on D[31:24] will be registered on the next rising edge of CLK. Clock H4 The MCF5206E negates the internal transfer acknowledge and CAS[0], ending the first byte read transfer. At this point, the new page has been opened; therefore, the MCF5206E continues to assert RAS. Once CAS[0] is negated, the DRAM disables its output drivers and D[31:0] is three-stated. The negation of CAS[0] begins the CAS precharge. Clock H5/L5 A byte read transfer to the same DRAM bank is generated internally by the ColdFire core. This transfer misses the open page. Clock H6 The ColdFire core initiated a DRAM transfer on the previous cycle that misses the open page. Therefore, the MCF5206E negates RAS, beginning the RAS precharge. Once the RAS precharge time has been reached, a transfer to a new page can start. Clock H7 The byte read transfer to a new page starts in H7. During H7, the MCF5206E drives the row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $1 indicating a byte transfer, and asserts TS. Clock L7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-29MCF5206E asserts RAS is to indicate the row address is valid on A[27:9]. Clock H8 The MCF5206E negates TS, and drives the column address on A[27:9]. Clock L8 The MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives data on D[31:24]. Clock H9 The internal transfer acknowledge asserts to indicate that the byte read transfer will be completed and data on D[31:24] will be registered on the next rising edge of CLK. Clock H10 The MCF5206E negates the internal transfer acknowledge and CAS[0], ending the first byte read transfer. At this point, the new page has been opened; therefore, the MCF5206E continues to assert RAS. Once CAS[0] is negated, the DRAM disables its output drivers and D[31:0] is three-stated. The negation of CAS[0] begins the CAS precharge. 11.3.4.5 BUS ARBITRATION. If the.com bus mastership while a page is MCF5206E loses open (RAS is asserted), RAS is precharged. The RAS precharge timing depends on whether an active fast page mode DRAM transfer is in progress, whether a non-DRAM transfer is in progress, or whether the external bus is idle. If the BL bit in the SIMR is cleared and BG is negated while an active fast page mode DRAM transfer is in progress, BD remains asserted until the transfer is complete. Once the DRAM transfer completes, the MCF5206E negates BD and begin precharging RAS. In the case where the BL bit in the SIMR is cleared and BG is negated while a nonDRAM transfer is in progress and a page is open, the MCF5206E begins precharging RAS on the cycle following the negation of BG, even though BD remains asserted until the completion of the nonDRAM transfer. If the BL bit in the SIMR is cleared and BG is negated while the external bus is idle and a page is open, the MCF5206E negates BD and begins precharging RAS on the cycle following the negation of BG. When the BL bit in the SIMR is set to 1 and BG is asserted, the bus is locked with the MCF5206E . If BG is negated while the bus is locked and a page is open, RAS and BD remains asserted, because the MCF5206E maintains bus mastership regardless of BG when the bus is locked.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives the row address on A[27:9], and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H2 The MCF5206E negates TS, and drives the column address on A[27:9]. Clock L2MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-31MCF5206E asserts CAS to indicate the column address is valid on A[27:9]. Clock H3 The internal transfer acknowledge asserts to indicate that the current transfer will be completed on the next rising edge of CLK. Clock H4 The MCF5206E negates the internal transfer acknowledge and CAS, ending the transfer. At this point, a page has been opened; therefore, the MCF5206E continues to assert RAS. The negation of CAS begins the CAS precharge. Clock H6 After the bus has idled for two clocks, BG is negated (while the BL bit in the SIMR is cleared). Clock H7 The MCF5206E then three-states the external bus signals, negates RAS (closing the page), and negates BD, relinquishing mastership of the bus. The negation of RAS begins the RAS precharge.MCF5206E negates RAS, closing the page. Because all secondary transfers of a burst are guaranteed to be page hits, a page miss never occurs in burst page mode. Nonburst transfers occur as in normal mode. Therefore, burst page mode always provides the same or better performance than normal mode. The timing of read and write transfers is identical in burst page mode, with the exception of when the DRAM drives data on reads and when the MCF5206E drives data on writes. The fastest possible burst transfer in burst page mode requires three clocks for the first transfer and two clocks on the secondary transfers. The fastest possible nonburst transfer in burst page mode requires three clocks. You can program the DCTR to generate slower burst page mode transfers. Figure 11-12 shows a longword write transfer followed by a word read transfer to a 16-bit port with burst page mode enabled for the bank. The burst longword write transfer is handled as in fast page mode with the initial word transfer of the burst taking three cycles and the secondary word transfer taking two cycles. However, in burst page mode, the MCF5206E precharges RAS once the burst transfer is complete. The second transfer (a word read) is executed as in normal mode as it is not a burst transfer.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E drives the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives SIZ[1:0] to $0 indicating a longword transfer, and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H2 The MCF5206E negates TS, drives the column address on A[27:9], and begins driving the data on D[31:16]. Clock L2 The MCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-33MCF5206E negates the internal transfer acknowledge, and CAS[1:0], ending the first word write transfer of the longword burst. At this point, the new page has been opened; therefore, the MCF5206E continues to assert RAS. The negation of CAS[1:0] begins the CAS precharge. The MCF5206E drives the next column address on A[27:9] and the next data on D[31:16]. Clock L4 The MCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. Clock H5 The internal transfer acknowledge asserts to indicate that the first word transfer of the longword burst will be completed on the next rising edge of CLK. Clock H6 The MCF5206E negates the internal .com transfer acknowledge, RAS, and CAS[1:0], ending the final write transfer of the longword burst. Because the bank is in burst page mode, MCF5206E precharges RAS at the end of the burst. The negation of RAS begins the RAS precharge. When the burst write is completed, the MCF5206E three-states D[31:0]. Clock H8 Clock H8 is the earliest the next transfer initiated by the ColdFire core can start. Because this next DRAM cycle is a nonburst word read transfer, it is handled as a normal mode transfer. During Clock H8, the MCF5206E drives the row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $2 indicating a word transfer, and asserts TS. Clock L8MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H9 The MCF5206E negates TS, and drives the column address on A[27:9]MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives the data on D[31:16]. Clock H10 The internal transfer acknowledge asserts to indicate that the current transfer will be completed and the data on D[31:16] will be registered on the next rising edge of CLK. Clock H11 The MCF5206E registers the read data driven by the DRAM, and negates the internal transfer acknowledge, RAS and CAS[1:0], ending the word read transfer. This begins the RAS precharge. Once CAS is negated, the DRAM disables its output drivers and D[31:0] is three-stated.MCF5206E supports EDO DRAM with a CAS timing that takes advantage of the read data remaining valid after CAS negates. To enable the EDO CAS timing for both DRAM banks, set the EDO Enable bit in the DCTR to 1. When set to 1, CAS negates one-half clock cycle earlier for fast-page-mode and burst-page-mode transfers than when the EDO Enable bit is cleared. At higher clock frequencies, the EDO CAS timing allows slower, less expensive EDO DRAMs to be used, since the CAS precharge starts before data is registered on read transfers. For the fastest timing in fast page mode or burst page mode, having the EDO Enable bit set gives one clock of CAS precharge time, rather than onehalf of a clock with the EDO Enable bit cleared. Since EDO DRAM continues to drive data after a read as long as RAS is asserted, be careful with the system design using EDO DRAM to ensure bus contention does not occur when a nonDRAM transfer occurs while a page is open in fast page mode. NOTE Failure to use normal mode or burst page mode with EDO DRAM without external circuitry to control the DRAM output drivers could result in damage to the MCF5206E and the system.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-35MCF5206E drives the row address on A[27:9], drives DRAMW high indicating a DRAM write transfer, drives SIZ[1:0] to $2 indicating a byte transfer, and asserts TS. Clock L1 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9].MCF5206E negates TS, drives the column address on A[27:9]. Clock L2 The MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the EDO DRAM drives data on D[31:24].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E to negate CAS[0] on L3 to allow more CAS precharge time. The negation of CAS[0] begins the CAS precharge. Clock H4MCF5206E negates the internal transfer acknowledge, ending the first byte read transfer of the word burst. At this point, the new page has been opened; therefore, the MCF5206E continues to assert RAS. The MCF5206E drives the next column address on A[27:9]. Clock L4 The MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point, the EDO DRAM begins driving the data on D[31:24]. Clock H5MCF5206E to negate CAS[0] on L3 to allow more CAS precharge time. The negation of CAS[0] begins the CAS precharge. Clock H6 The MCF5206E negates the internal transfer acknowledge, ending the final byte read transfer of the word burst. Because the bank is in fast page mode, MCF5206E continues to assert RAS. Because RAS remains asserted, the EDO DRAM continues to drive the data from the previous read transfer on D[31:24]. Clock H7/L7 A byte read transfer to the same DRAM bank is generated internally by the ColdFire core. This transfer misses the open page.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-37MCF5206E negates RAS, beginning the RAS precharge. Once the RAS precharge time has been reached, a transfer to a new page can start. Once RAS is negated, the EDO DRAM disables its output drivers and D[31:0] is three-stated. Clock H9 The byte read transfer to a new page starts in H9. During H9, the MCF5206E drives the row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $1 indicating a byte transfer, and asserts TS. Clock L9 Now that the RAS precharge time has been reached, the MCF5206E asserts RAS is to indicate the row address is valid on A[27:9]. Clock H10 The MCF5206E negates TS, drives the column address on A[27:9]. Clock L10 The MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this .com point the EDO DRAM drives data on D[31:24]. Clock H11 The internal transfer acknowledge asserts to indicate that the first byte read transfer of the word burst will be completed and the data on D[31:24] will be registered on the next rising edge of CLK. Clock H12 The MCF5206E negates the internal transfer acknowledge, ending the byte-read transfer. Because the bank is in fast page mode, MCF5206E continues to assert RAS. Because RAS remains asserted, the EDO DRAM continues to drive the data from the previous read transfer on D[31:24].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E is not the bus master, bus request (BR) is not asserted until after the refresh completes. A master reset terminates any active refresh cycle and resets the refresh controller. Master reset is required on all power-on resets. During a master reset, refresh cycles do not occur; after a master reset, refreshes occur at the slowest rate (DCRR is initialized to $0000).MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-39MCF5206E registers all available address signals, R/W, and SIZ[1:0] on the rising edge of clock when TS is asserted. Based on the address, direction, and data size, the DRAMC asserts RAS, CAS, DRAMW, and conditionally drives the address bus.MCF5206E DRAMC to respond on external master transfers, TS should not be asserted to the MCF5206E during external master transfers. However, the MCF5206E continues to generate DRAM refresh cycles while the bus is granted to an external master. NOTE The driving of the data on writes and the latching of data on reads based on the data size and port size of the DRAM is the responsibility of the external master. The MCF5206E does not drive the data bus when it is not master of the external bus. The MCF5206E can delay the access to DRAM for an external master initiated transfer if a refresh request is pending or if the programmed RAS precharge time has not been reached. If there is a refresh cycle in progress or if there is a refresh request pending when an external master starts a DRAM transfer, the MCF5206E does not start driving the row address and assert RAS until the RAS precharge time has been reached after completing the refresh cycle. If a refresh request occurs during an external master DRAM transfer, the refresh cycle is delayed until the external master DRAM transfer is completed. If the programmed RAS precharge time from the previous DRAM transfer has not beenMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E does not start driving the row address and assert RAS until the precharge time has been reached. For external master DRAM transfers, the MCF5206E drives TA as an output. TA is asserted to signify the end of each transfer (or subtransfer in the case of a burst). The assertion of TA can be used for latching data on read transfers and can also be used by the external master to trigger the driving of new write data for successive transfers during bursts. When using the MCF5206E to multiplex the address for external master DRAM transfers (DAEM bit in the DCTR is set), the external master must stop driving the address bus during the clock cycle after TS is asserted. This allows the MCF5206E to drive the row address and the column address on A[27:9] at the appropriate times. If the external master cannot three-state the address bus, the driving of the address by the MCF5206E should be disabled and the address multiplexing for external master transfers must be handled in the external system. If address multiplexing for external master transfers is to be handled in the external system, the DRAMC must be configured to three-state the address bus during these transfers by clearing the DAEM bit in the DCTR. This does not affect the operation of TA, RAS, CAS, or DRAMW during external master DRAM transfers. NOTE The MCF5206E does not drive the address for external master .com chip select or default memory transfers. 11.3.8.1 EXTERNAL MASTER NONBURST TRANSFER IN NORMAL MODE. An external master nonburst transfer to DRAM is generated when the operand size is the same or smaller than the DRAM port size (e.g., longword transfer to a 32-bit port or byte transfer to a 16-bit port). The external master must assert TS at the start of all non-burst transfers. The timing of nonburst reads and nonburst writes is identical in normal page mode, with the exception of when the DRAM drives data on reads and when the external master drives data on writes. The fastest possible nonburst transfer in normal mode requires 5 clocks. You can program the DCTR to generate slower normal mode transfers.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-41MCF5206E must be set up with respect to the rising edge of CLK H2. Clock H2 On the rising edge of CLK when TS is asserted, the MCF5206E registers the address and attribute signals. The MCF5206E internally decodes these signals and determine if the external master transfer is a DRAM access. The external master negates TS and must three-state A[27:0] after the rising edge of CLK H2, if the internal address multiplexing is to be used.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E has determined that the external master transfer is a DRAM access, so the MCF5206E drives A[27:0] with the same value as was registered on the rising edge of H2. A[27:9] contains the DRAM row address. The MCF5206E also drives DRAMW high, indicating a DRAM read cycle. Clock L3 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H4 The MCF5206E internally multiplexes the address and drives out the column address on A[27:9]. The MCF5206E also actively drives TA negated. Clock L4 The MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives the data on D[31:24]. Clock H5 The MCF5206E asserts the TA signal to indicate that the byte read transfer will be completed and the read data will be valid on D[31:24] on the next rising edge of CLK. Clock H6MCF5206E then negates RAS, CAS[0], and TA and three-states A[27:0], ending the byte-read transfer. The negation of RAS starts the RAS precharge. Once A[27:0] has three-stated, the external master can start another transfer. In this case, the external master starts a DRAM byte write transfer immediately by driving A[27:0], driving R/W low indicating a write transfer, driving SIZ[1:0] to $1 indicating a byte transfer, and asserting TS. The external master must drive the data in the correct byte lanes based on the data size and the port size of the DRAM, and must drive the data to meet the timing specifications of the DRAM. In this case, the external master should drive the write data on D[31:24]. Clock H7 The MCF5206E three-states TA. On the rising edge of CLK where TS is asserted, the MCF5206E registers the address and attribute signals. The MCF5206E internally decodes these signals and determines if the external master transfer is a DRAM access. The external master must three-state A[27:0] after the rising edge of CLK H2, if the internal address multiplexing is to be used.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-43MCF5206E has determined that the external master transfer is a DRAM access, so the MCF5206E drives the A[27:0] with the same value as was registered on the rising edge of H2. A[27:9] contains the row address for the DRAM. The MCF5206E also drives DRAMW low, indicating a DRAM write cycle. Clock L8 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H9 The MCF5206E internally multiplexes the address and drives out the column address on A[27:9]. The MCF5206E also actively drives TA negated. Clock L9 The MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. The external master must set up and hold the data with respect to the falling edge of CAS[0] based on the DRAM specifications. Clock H10 The MCF5206E asserts the TA signal to indicate that the byte write transfer will be .com completed on the next rising edge of CLK. Clock H11 The MCF5206E then negates RAS, CAS[0], and TA, and three-state the address bus, ending the byte write transfer. The negation of RAS starts the RAS precharge. Once A[27:0] has three-stated, the external master can start another transfer. Clock H12 The MCF5206E three-states TA. 11.3.8.2 EXTERNAL MASTER BURST TRANSFER IN NORMAL MODE. A burst transfer to DRAM is generated when the operand size is larger than the DRAM bank port size (e.g., line transfer to a 32-bit port, longword transfer to an 8-bit port). On DRAM burst transfers, the external master should assert TS only once. The start of the secondary transfers of a burst is delayed by the DRAMC until the programmed RAS precharge time is met. The timing of external master burst reads and burst writes is identical in normal page mode, with the exception of when the DRAM drives data on reads and when the external master drives data on writes.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E . The MCF5206E asserts RAS after the RAS precharge time is met and the transfer completes the same as in the nonburst case. Driving the write data in the correct byte lanes at the proper time to meet the specifications of the DRAM is the responsibility of the external master.MCF5206E must be set up with respect to the rising edge of CLK H2. The external master must drive the dataMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-45MCF5206E registers the address and attribute signals. It internally decodes these signals and determines if the external master transfer is a DRAM access. The external master negates TS and must three-state A[27:0] after the rising edge of CLK H2, if the internal address multiplexing is to be used. Clock H3 The MCF5206E has determined that the external master transfer is a DRAM access, so the MCF5206E drives A[27:0] with the same value as was registered on the rising edge of H2. A[27:9] contain the DRAM row address. The MCF5206E also drives DRAMW low indicating a DRAM write cycle. Clock L3 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H4MCF5206E internally multiplexes the address and drives out the column address on A[27:9]. The MCF5206E also actively drives TA negated.MCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. The external master must set up and hold the first word of data on D[31:16] with respect to the falling edge of CAS[1:0] based on the DRAM specifications. Clock H5 The MCF5206E asserts the TA signal to indicate that the first word write transfer of the longword burst will be completed on the next rising edge of CLK. Clock H6 The MCF5206E negates RAS, CAS[1:0], and TA, ending the first word transfer of the longword burst. The negation of RAS starts the RAS precharge. The MCF5206E drives the row address again for second word transfer of the longword burst write. Clock L7 Once the RAS precharge time has been met, the MCF5206E asserts RAS to indicate the row address is valid on A[27:9].MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E internally increments and multiplexes the address and drives out the column address on A[27:9] for the second word transfer of the longword burst write. Clock L8 Clock L8 is the same as Clock L4. The MCF5206E asserts CAS[1:0] to indicate the column address is valid on A[27:9]. The external master must set up and hold the second word of data on D[31:16] with respect to the falling edge of CAS[1:0] based on the DRAM specifications. Clock H9MCF5206E asserts the TA signal to indicate that the second word write transfer of the longword burst will be completed on the next rising edge of CLK. Clock H10 The MCF5206E negates RAS, CAS[1:0], and TA, and three-states A[27:0], ending the second word transfer of the longword burst. The negation of RAS starts the RAS precharge. Once A[27:0] has three-stated, the external master can start another transfer. Clock H11 The MCF5206E three-states TA.MCF5206E negates RAS, closing the page. Because all secondary transfers of a burst are guaranteed to be page hits, a page miss never occurs in burst page mode. Nonburst transfers occur as in normal mode (for nonburst transfers in burst page mode, refer to Section 11.3.8.1 External Master Non Burst Transfer in Normal Mode). Therefore, burst page mode always provides the same or better performance than normal mode. Because the DRAMC does not support fast page mode for external master transfers, a DRAM bank programmed for either burst page mode or fast page mode operates as burst page mode. The timing of read transfers and write transfers is identical in burst page mode, with the exception of when the DRAM drives data on reads and when the external master drives data on writes. The fastest possible external master burst transfer in burst page mode requires 5 clocks for the first transfer of the burst and two clocks for the secondary transfers. The fastestMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-47MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E must be set up with respect to the rising edge of CLK H2. Clock H2 On the rising edge of CLK when TS is asserted, the MCF5206E registers the address and attribute signals. It internally decodes these signals and determines if the external master transfer is a DRAM access. The external master negates TS and must three-state A[27:0] after the rising edge of CLK H2, if the internal address multiplexing is to be used. Clock H3 The MCF5206E has determined that the external master transfer is a DRAM access, so the MCF5206E drives A[27:0] with the same value as was registered on the rising edge of H2. A[27:9] contain the DRAM row address. The MCF5206E also drives DRAMW high indicating a DRAM read cycle. Clock L3 The MCF5206E asserts RAS to indicate the row address is valid on A[27:9]. Clock H4 The MCF5206E internally multiplexes the address and drives out the column address on A[27:9]. The MCF5206E also actively drives TA negated. Clock L4MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives the data on D[31:24]. Clock H5 The MCF5206E asserts the TA signal to indicate that the first byte read transfer of the burst will be completed and the read data will be valid on D[31:24] on the next rising edge of CLK. Clock H6 The MCF5206E negates CAS[0], and TA, ending the first byte read transfer of the burst. Because the bank is in burst page mode, the MCF5206E continues to assert RAS. The negation of CAS[0] starts the CAS precharge. The MCF5206E drives the column address on A[27:9] for second byte read transfer of the burst. Clock L6 After the CAS precharge time is met, the MCF5206E asserts CAS[0] to indicate the column address is valid on A[27:9]. At this point the DRAM drives the data bus.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-49MCF5206E asserts the TA signal to indicate that the first byte read transfer of the burst will be completed and the read data will be valid on D[31:24] on the next rising edge of CLK. Clock H8 The MCF5206E negates RAS, CAS[0], and TA, and three-states A[27:0], ending the final byte read transfer of the burst. Because the bank is in burst page mode, MCF5206E negates RAS when the burst transfer is completed. The negation of RAS starts the RAS precharge. Once A[27:0] has three-stated, the external master can start another transfer. Clock H9 The MCF5206E three-states TA. 11.3.8.4 LIMITATIONS. Because the external and internal address buses differ in size and address multiplexing occurs for transfers to DRAM, certain limitations exist for external master use of the DRAMC. * Fast page mode is not available for external master transfers. If a bank has this featured enabled, then burst page mode is used for external master transfers and fast page mode is used for ColdFire core-initiated transfers. * The UC, UD, SC, and SD mask bits are ignored during external master-initiated transfers. Therefore, if UC, UD, SC, and SD are all masked, that bank is available for external master transfers even though the bank is unavailable for ColdFire coreinitiated transfers. * In determining whether an external master transfer address hits in a DRAM bank, the bits of the internal address bus which are unavailable externally are regarded as $0. A[31:28] are always be set to $0 and A[27:24] are conditionally (based on PAR) be set to $0. In order for a bank to be accessible for external-master transfers, the address bits that are unavailable to the external master must either be set to 0 in the DCAR or be masked in the DCMR. * DRAM bank size is limited by the availability of A[27:24] as determined by the PAR control register.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-51MCF5206E output driver enables for the external address bus during external master transfers that hit in DRAM address space. If DAEM is set to 1, the portion of A[27]/CS[7]/WE[0], A[26]/CS[6]/WE[1], A[25]/CS[5]/WE[2], A[24]/CS[4]/WE[3] that are configured as address signals are driven along with A[23:0] to provide row and column address multiplexing for external masters. This field does not affect the address multiplexing for DRAM transfers initiated by the ColdFire core. 0 = Do not drive the external address signals as outputs during external master DRAM transfers 1 = Drive the external address signals as outputs to provide row and column address multiplexing during external master DRAM transfers EDO - Extended Data-Out Enable This field controls page mode CAS timing. If the DRAM banks are populated with extended data-out DRAM, the EDO Enable bit can be set to take advantage of the CAS timing allowed by EDO DRAMs. The EDO Enable bit, along with the CAS and CP bits,MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-53MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-55MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-57MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-59MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E internal modules at address $00004000. Then the DRAM Controller Timing Register (DCTR) is initialized to give the fastest possible DRAM transfer waveform timing. The DRAM Controller Refresh Register (DCRR) is then written causing DRAM refresh cycles to be generated once every 512 clocks (12.8 sec for a 40 MHz system clock/9.5 sec for a 54 MHz system clock). Once the DCRR is written, a refresh cycle is immediately generated and refresh cycles are generated at the newly programmed rate. Next, DRAM Controller Address Register 0 (DCAR0) is written, making the starting address of DRAM bank 0 $00100000. DRAM Controller Mask Register 0 (DCMR0) is then written such that transfer address bits 18 - 16 are masked, making the DRAM bank 0 address space 1 MByte. Therefore, DRAM bank 0 address space rangesMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 11-61MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E contains two universal asynchronous/synchronous receiver/transmitters (UARTs) that act independently. Each UART is clocked by the system clock, which eliminates the need for an external crystal. This section applies to both UARTs, which are identical. Refer to Section 12.4 for addressing differences. Each UART module, shown in Figure 12-1, consists of the following major functional areas: * Serial Communication ChannelMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-1MCF5206E contains two independent UART modules. Features of each UART module include the following: * UART clocked by the system clock or external clock (TIN) * Full duplex asynchronous/synchronous receiver/transmitter channel * Quadruple-buffered receiver * Double-buffered transmitter * Independently programmable baud rate for receiver and transmitter selectable from: -- timer-generated baud rate or external clockMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E timer for use as a synchronous or asynchronous clocking source for the UART. The baud-rate timer is part of each UART and not related to the ColdFire timer modules.MCF5206E interrupt controller of an interrupt condition. The output is the logical NOR of all (as many as four) unmasked interrupt status bits in the UART Interrupt Status Register (UISR). You program the UART Interrupt Mask Register (UIMR) to determine which interrupts will be valid in the UISR. You program the UART module interrupt level in the MCF5206E interrupt controller external to the UART module. You can configure the UART to supply the vector from the UART Interrupt Vector Register (UIVR) or program the SIM to provide an autovector when a UART interrupt is acknowledged. You can also program the interrupt level, priority within the level, and autovectoring capability in the SIM register ICR_U1.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E timer module that is integrated on the bus of the ColdFire core. The UART has a baud generator based on an internal baud-rate timer that is dedicated to the UART. You can program the Clock Select Register (USCR) to enable the baud-rate timer or an external clock source from TIN to generate baud rates. When the baud-rate timer is used, a prescaler supplies an asynchronous 32x clock source to the baud-rate timer. The baudrate timer register value is programmed with the UBG1 and UBG2 registers. See Section 12.4.1.12 Timer Upper Preload Register 1 (UBG1) and Section 12.4.1.13 Timer Upper Preload Register 2 (UBG2) for more information. An external TIN clock source, when enabled in the USCR, can generate an x1 or x16 asynchronous or synchronous clock to the UART receiver and transmitter. Figure 12-3 shows the relationship of clocking sources.MCF5206E TIMERMCF5206E UART BAUD RATE OUTPUT PROGRAMMED IN USCR x1 PRESCALAR BAUD RATE TINMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-11MCF5206E Pin Assignment Register (PAR) in the SIM to enable the corresponding I/O pins for these functions. If the FIFO stack contains characters and the receiver is disabled, the CPU can still read the characters in the FIFO. If the receiver is reset, the FIFO stack and all receiver status bits, corresponding output ports, and interrupt request are reset. No additional characters are received until the receiver is re-enabled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-15MCF5206E system clock is also used for the UART module. The UART module responds to reads with byte data on D[7:0]. Reserved registers return logic zero during reads. 12.3.5.2 WRITE CYCLES. The CPU with zero wait states accesses the UART module. The UART module accepts write data on D[7:0]. Write cycles to read-only registers and reserved registers complete in a normal manner without exception processing; however, the data is ignored. 12.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The UART module can arbitrate for interrupt servicing and supply the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt vector register (UIVR) must be initialized. The interrupt vector number generated by the IVR is used if the autovector is not enabled in the SIM Interrupt Control Register (ICR). If the UIVR is not initialized and the ICR is not programmed for autovector, a spurious interrupt exception is taken if interrupts are generated. This works in conjunction with the MCF5206E interrupt controller, which allows a programmable Interrupt Priority Level (IPL) .com for the interrupt.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-17MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-19MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-21MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-23MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-25MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-27MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-29MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-31MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-33MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-35MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-37MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 12-39MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-3MCF5206E is master, it must not transmit an address that is equal to its slave address. The MCF5206E cannot be master and slave at the same time. Only the slave with a calling address that matches the one transmitted by the master will responds by returning an acknowledge bit by pulling the SDA low at the 9th clock (see Figure 13-2).MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 13-15MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E contains two general-purpose16-bit timers. This section of the manual documents how the 16-bit timers operate.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 14-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 14-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 14-5MCF5206E . With a 54MHZ clock, the maximum period is 5 seconds and a resolution of 18.5 ns. They can be free running or count to a value and reset. The following examples set up the timers: Timer 1 will count to $AFAF, toggle its output, and reset back to $0000. This will continue infinitely until the timer is disabled or a reset occurs. No interrupts are set. Prescale is set at 256 and the system clock is divided by 16, therefore resolution is (16*(256))/25MHz = 163.84us. Timeout period is (16*256*44976)/25mhz = 7.369s. ($0 - $AFAF = 44976 decimal) Timer 2 will be free-running and send out a logic pulse every time it compares the count value in the TRR register. value, which for now, is randomly chosen as $1234. Prescale is set at 127 with the sys_clock initially divided by 16 (by setting bits 2&1 of the TMR register to 10 therefore, resolution is (16*(127))/25mhz = 81.28us. Interrupts are NOT enabled.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 14-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 14-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-1MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-15MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-17MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-19MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-21MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-23MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-25MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-27MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-29MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-31MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-33MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-35MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 15-37MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E includes dedicated user-accessible test logic that is fully compliant with the IEEE standard 1149.1 Standard Test Access Port and Boundary Scan Architecture. Use the following description in conjunction with the supporting IEEE document listed above. This section includes the description of those chip-specific items that the IEEE standard requires as well as those items specific to the MCF5206E implementation. The MCF5206E JTAG test architecture implementation currently supports circuit board test strategies that are based on the IEEE standard. This architecture provides access to all of the data and chip control pins from the board edge connector through the standard four-pin test access port (TAP) and the active-low JTAG reset pin, TRST. The test logic itself uses a static design and is wholly independent of the system logic, except where the JTAG is subordinate to other complimentary test modes (see Section 15: Debug Support section for more information). When in subordinate mode, the JTAG test logic is placed in reset and the TAP pins can be used for other purposes in accordance with the rules and restrictions set forth using a JTAG compliance-enable pin. The MCF5206E JTAG implementation can:MCF5206E device by reducing the shift register path to a single cell * Sample the MCF5206E system pins during operation and transparently shift out the result * Set the MCF5206E output drive pins to fixed logic values while reducing the shift register path to a single cell * Protect the MCF5206E system output and input pins from backdriving and random toggling (such as during in-circuit testing) by placing all system signal pins to highimpedance state NOTE The IEEE Standard 1149.1 test logic cannot be considered completely benign to those planning not to use JTAG capability. You must observe certain precautions to ensure that this logic does not interfere with system or debug operation. Refer to Section 16.6 Disabling the IEEE 1149.1 Standard Operation.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 16-1MCF5206E implementation of the 1149.1 IEEE Standard. The test logic includes several test data registers, an instruction register, instruction register control decode, and a 16-state dedicated TAP controller.MCF5206E JTAG pin is defined to be a compliance-enable input per Section 3.8 of the IEEE Standard 1149.1a-1993 entitled "Subordination of this Standard within a Higher Level Test Strategy." When JTAG is a logic 0, the MCF5206E is in JTAG mode; when JTAG is a logic 1, the MCF5206E is in Debug mode.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E IEEE 1149.1 Standard implementation uses a 3-bit instruction-shift register without parity. This register transfers its value to a parallel hold register and applies one of six possible instructions on the falling edge of TCK when the TAP state machine is in the update-IR state. To load the instructions into the shift portion of the register, place the serial data on the TDI pin prior to each rising edge of TCK. The MSB of the instruction shift register is the bit closest to the TDI pin and the LSB is the bit closest to the TDO pin.MCF5206E implementation supports and are described in the 1149.1. 16.3.1.1 EXTEST INSTRUCTION. The external test instruction (EXTEST) selects the boundary-scan register. The EXTEST instruction forces all output pins and bidirectional pins configured as outputs to the preloaded fixed values (with the SAMPLE/PRELOAD instruction) and held in the boundary-scan update registers. The EXTEST instruction canMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 16-3MCF5206E to determine its version number and other part identification data. The IDcode register has been implemented in accordance with IEEE 1149.1 so that the least significant bit of the shift register stage is set to logic 1 on the rising edge of TCK following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the IDcode register is always a logic 1. The remaining 31-bits are also set to fixed values (see 16.3.2 IDCode Register) on the rising edge of TCK following entry into the capture-DR state. The IDCODE instruction is the default value placed in the instruction register when a JTAG reset is accomplished by either asserting TRST or holding TMS high while clocking TCK through at least five rising edges and the falling edge after the fifth rising edge. A JTAG reset causes the TAP state machine to enter the test-logic-reset state (normal operation of the TAP state machine into the test-logic-reset state also results in placing the default value of octal 1 into the instruction register). The shift register portion of the instruction register is loaded with the default value of octal 1 when in the Capture-IR state and a rising edge of TCK occurs. 16.3.1.3 SAMPLE/PRELOAD INSTRUCTION. The SAMPLE/PRELOAD instruction .com provides two separate functions. First, it obtains a sample of the system data and control signals present at the MCF5206E input pins and just prior to the boundary scan cell at the output pins. This sampling occurs on the rising edge of TCK in the capture-DR state when an instruction encoding of octal 4 is resident in the instruction register. You can observe this sampled data by shifting it through the boundary-scan register to the output TDO by using the shift-DR state. Both the data capture and the shift operation are transparent to system operation. You are responsible for providing some form of external synchronization to achieve meaningful results because there is no internal synchronization between TCK and the system clock, CLK. The second function of the SAMPLE/PRELOAD instruction is to initialize the boundary scan register update cells before selecting EXTEST or CLAMP. This is achieved by ignoring the data being shifted out of the TDO pin while shifting in initialization data. The update-DR state in conjunction with the falling edge of TCK can then transfer this data to the update cells. This data will be applied to the external output pins when one of the instructions listed above is applied. 16.3.1.4 HIGHZ INSTRUCTION. The HIGHZ instruction anticipates the need to backdrive the output pins and protect the input pins from random toggling during circuit board testing. The HIGHZ instruction selects the bypass register, forcing all output and bidirectional pins to the high-impedance state.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E processor becomes the device under test on a board design with multiple chips on the overall 1149.1 defined boundary-scan chain. The bypass register has been implemented in accordance with 1149.1 so that the shift register stage is set to logic zero on the rising edge of TCK following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the bypass register is always a logic zero (to differentiate a part that supports an IDCODE register from a part that supports only the bypass register). The BYPASS instruction goes active on the falling edge of TCK in the update-IR state when the data held in the instruction shift register is equivalent to octal 7.MCF5206E . The MCF5206E JTAG instruction encoded as octal 1 provides for reading the JTAG IDcode register. The format of this register is defined below.MCF5206E . Bits 27-22 Design Center Indicates the ColdFire design center. Bits 21-12 Device Number Indicates an MCF5206E .MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 16-5MCF5206E model includes an IEEE 1149.1-compliant boundary-scan register. The boundary-scan register is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. This register captures signal pin data on the input pins, forces fixed values on the output signal pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins. Boundary scan bit definitions The latest (and most accurate) version of the boundary scan bit definitions can be downloaded from the ColdFire homepage on the Motorola website http://www.motorola.com/ColdFireMCF5206E includes an IEEE 1149.1-compliant bypass register, which creates a single bit shift register path from TDI to the bypass register to TDO when the BYPASS instruction is selected.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 16-7MCF5206E .MCF5206E can be used without the IEEE 1149.1 test logic being active: 1) Nonuse of the JTAG test logic by either nontermination (disconnection) or intentional fixing of TAP logic values, and 2) Intentional disabling of the JTAG test logic by assertion of the JTAG signal (entering Debug mode). There are several considerations that must be addressed if the IEEE 1149.1 logic is not going to be used once the MCF5206E is assembled onto a board. The prime consideration is to ensure that the IEEE 1149.1 test logic remains transparent and benign to the system logic during functional operation. This requires the minimum of either connecting the TRST pin to logic 0, or connecting the TCK clock pin to a clock source that will supply five rising edges and the falling edge after the fifth rising edge, to ensure that the part enters the test-logic-reset state. The recommended solution is to connect TRST to logic 0. Another consideration is that the TCK pin does not have an internal pullup as is required on the TMS, TDI, and TRST pins; therefore, it should not be left unterminated to preclude mid-level input values. Figure 16-3 shows pin values recommended for disabling JTAG with the MCF5206E in JTAG mode (JTAG=0).MCF5206E without the IEEE 1149.1 logic being active is to select debug mode by placing a logic 1 on the defined compliance enable pin, JTAG. When JTAG is a logic 1, then the IEEE 1149.1 test controller is placed in the test-logicreset state by the internal assertion of the TRST signal to the controller, and, the TAP pins function as Debug mode pins. While in JTAG mode, input pins TDI/DSI, TMS/BKPT, andMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E in Debug mode.MCF5206E BSDL DESCRIPTIONMCF5206E BSDL description is available on the World Wide Web at http://www.mot.com/coldfireMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 16-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E device may be subjected without being damaged. However, the device cannot operate normally while being exposed to these electrical extremes. This device contains circuitry that protects against damage from high static voltages or electrical fields; however, you should take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this highimpedance circuit. Operational reliability improves when unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VDD).MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-1MCF5206E processor.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-5MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-7MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-9MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-11MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-13MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-15MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-17MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-19MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 17-21MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E is supplied in a 160-pin plastic quad flat pack package as shown:MCF5206E FT Top ViewMCF5206E processor.MCF5206E Package Diagram & PinoutMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E Package/Frequency AvailabilityMCF5206E MCF5206E information is available on the WWW at http://sps.motorola.com/coldfire. Hard copy information is available from Motorola literature distribution centers. Table 18-2. MCF5206E DocumentationMCF5206E /D MCF5206E UM/D MCF5200PRM/AD Document Title MCF5206E Product Brief (Currently available) MCF5206E User's Manual (Est. Stocking LDC July 98) MCF5200 ColdFire Family Programmer's Reference Manual Rev. 1.0 (Currently available)MCF5206E processor consist of a complete suite of compilers and debuggers available from third-party developers, as shown in the tables below. Any development tool that generates code for the Motorola ColdFire MCF5206 can do the same for the MCF5206E processor.MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com 18-3MCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E MEMORY MAP SUMMARYMCF5206E . Table A-1. MCF5206E User Programming ModelMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.comMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Appendix A-iiiMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Appendix B-iMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Appendix B-iiiMCF5206E USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com Index-1MCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com Index-3MCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com Index-5MCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLAMCF5206E User's Manual For More Information On This Product, Go to: www.freescale.com Index-7MCF5206E Memory Map Appendix B: Porting from M68000 A BMCF5206E Memory Map Appendix B: Porting from M68000
